Read algorithms for three-dimensional crosspoint memory architectures
In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.
1. A non-volatile memory device comprising:
a memory array comprising:
a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; and
address lines to apply voltages across the memory cells, wherein each memory cell has a corresponding address line pair to apply voltages thereto; and
memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of the address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.
2. The memory device of claim 1 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.
3. The memory device of claim 2 , wherein the predetermined voltage is between −2.8V and −3.4 V.
4. The memory device of claim 1 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.
5. The memory device of claim 4 , wherein the predetermined voltage is between 3.2V and 3.7V.
6. The memory device of claim 1 , wherein the memory controller circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.
7. A memory module comprising:
input/output (I/O) circuitry to couple the memory module with an external controller; and
a plurality of non-volatile memory devices, each memory device comprising:
a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region;
address lines to apply voltages across the memory cells, wherein each memory cell has a corresponding address line pair to apply voltages thereto; and
memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of the address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.
8. The memory module of claim 7 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.
9. The memory module of claim 8 , wherein the predetermined voltage is between −2.8V and −3.4 V.
10. The memory module of claim 7 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.
11. The memory module of claim 10 , wherein the predetermined voltage is between 3.2V and 3.7V.
12. The memory module of claim 7 , wherein the memory controller circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.
13. A memory controller comprising:
circuitry interface with address lines of a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.
14. The memory controller of claim 13 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.
15. The memory controller of claim 14 , wherein the predetermined voltage is between −2.8V and −3.4 V.
16. The memory controller of claim 13 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.
17. The memory controller of claim 16 , wherein the predetermined voltage is between 3.2V and 3.7V.
18. The memory controller of claim 13 , wherein the circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.
19. A method of reading a state in a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the method comprising:
ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.
20. The method of claim 19 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.
21. The method of claim 20 , wherein the predetermined voltage is between −2.8V and −3.4 V.
22. The method of claim 19 , wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.
23. The method of claim 22 , wherein the predetermined voltage is between 3.2V and 3.7V.
24. The method of claim 19 , wherein the differential voltage between the first and second address lines is between 5.7V and 6.2V and the determined memory state is a state having a crystalline PM region and a crystalline SD region.
25. The method of claim 19 , wherein the differential voltage between the first and second address lines is between 6.3V and 6.8V and the determined memory state is a state having a crystalline PM region and an amorphous SD region.