IP Library › Granted Patent US 12,119,289
Granted Patent B2
US 12,119,289 · App. 18/328,896 · Granted Oct 15, 2024

Semiconductor packages with roughened conductive components

Inventors: Yee Gin Tea (Bukit Katil, MY); Chong Han Lim (Seri Kembangan, MY)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L23/49548H01L21/4825H01L21/4828H01L21/565H01L23/3107H01L23/3114H01L23/49503H01L23/49513H01L23/4952H01L23/49541H01L23/49582H01L24/06H01L24/29H01L24/49H01L2924/181
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Quick Facts
Patent No.
US 12,119,289
App. No.
18/328,896
Granted
Oct 15, 2024
Kind
B2
Abstract

In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.

Claims (35)

1. A semiconductor package, comprising:

a die pad with a first roughened conductive surface;

a conductive lead with a second roughened conductive surface, wherein the first and second roughened conductive surfaces include nodules of non-precious metal;

a semiconductor die disposed over the first roughened conductive surface; and

a bond wire coupling the semiconductor die to the second roughened conductive surface, the bond wire directly coupled to the second roughened conductive surface.

2. The semiconductor package of claim 1 , wherein the first and second roughened conductive surfaces have a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2.

3. The semiconductor package of claim 1 , wherein the bond wire fills an orifice in the second roughened conductive surface.

4. The semiconductor package of claim 1 , wherein the bond wire covers a protrusion of the second roughened conductive surface.

5. The semiconductor package of claim 1 , further comprising:

a mold compound encapsulating the die pad, the semiconductor die, and at least a portion of the conductive lead.

6. The semiconductor package of claim 5 , wherein the mold compound covers a protrusion of the second roughened conductive surface.

7. The semiconductor package of claim 5 , wherein the mold compound fills an orifice in the second roughened conductive surface.

8. The semiconductor package of claim 5 , wherein the mold compound forms a housing of the semiconductor package, and wherein the second roughened conductive surface terminates inside the housing.

9. The semiconductor package of claim 8 , wherein the conductive lead includes a part extended outside the housing, and wherein the part extended outside the housing has a surface that is even or smooth.

10. The semiconductor package of claim 1 , wherein an anti-tarnish layer covers the first roughened conductive surface.

11. The semiconductor package of claim 10 , wherein the anti-tarnish layer includes potassium sorbate, sodium dodecyl sulfate, sodium molybdate, benzotriazole, or a combination thereof.

12. The semiconductor package of claim 10 , further comprising:

an adhesive layer disposed between the anti-tarnish layer and the semiconductor die.

13. The semiconductor package of claim 1 , wherein the nodules of non-precious metal are plated on the die pad and on the conductive lead, respectively.

14. The semiconductor package of claim 1 , wherein the first and second roughened conductive surfaces include a copper-iron alloy.

15. A semiconductor package, comprising:

a conductive lead with a roughened conductive surface including nodules of non-precious metal;

a solder ball directly coupled to the roughened conductive surface of the conductive lead; and

a semiconductor die attached to the solder ball, the semiconductor die including a surface with a circuit formed therein, wherein the surface of the semiconductor die faces the solder ball.

16. The semiconductor package of claim 15 , wherein the roughened conductive surface has a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2.

17. The semiconductor package of claim 15 , wherein the solder ball fills an orifice in the roughened conductive surface.

18. The semiconductor package of claim 15 , wherein the solder ball covers a protrusion of the roughened conductive surface.

19. The semiconductor package of claim 15 , further comprising:

a mold compound encapsulating the semiconductor die, the solder ball, and at least a portion of the conductive lead.

20. The semiconductor package of claim 19 , wherein the mold compound covers a protrusion of the roughened conductive surface.

21. The semiconductor package of claim 19 , wherein the mold compound fills an orifice in the roughened conductive surface.

22. The semiconductor package of claim 19 , wherein the mold compound forms a housing of the semiconductor package, the roughened conductive surface terminating inside the housing.

23. The semiconductor package of claim 19 , wherein the semiconductor package is a quad flat no-lead (QFN) style package.

24. The semiconductor package of claim 15 , wherein the roughened conductive surface includes a copper-iron alloy.

25. The semiconductor package of claim 15 , wherein the nodules of non-precious metal are plated on the conductive lead.

Continuity (3)
Continuation 17157557 · Jan 25, 2021
Provisional Application 63133087 · Dec 31, 2020
Related Publication 20230317569A1 · Oct 5, 2023
Cited By (1)
US 12,424,525