Storage device using wafer-to-wafer bonding and method of manufacturing the same
A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.
1. A storage device including a non-volatile memory device, the non-volatile memory device comprising:
a first substrate including a first peripheral circuit region, the first peripheral region including a row decoder configured to select one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array; and
a second substrate including a second peripheral circuit region, the second peripheral circuit region including a page buffer unit configured to select at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region,
wherein the 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.
2. The storage device of claim 1 , wherein the page buffer unit extends in a second direction that is normal to a first direction.
3. The storage device of claim 2 , wherein the row decoder comprises a plurality of sub row decoders spaced apart from one another in the second direction to extend in the first direction.
4. The storage device of claim 3 , wherein
the 3D memory cell array comprises a plurality of memory blocks, and
each of the plurality of sub row decoders is arranged at an equal interval, in groups of four, with respect to each of the plurality of memory blocks.
5. The storage device of claim 2 , wherein
the row decoder comprises:
a plurality of first sub row decoders, spaced apart from one another in the second direction in a first row of the first peripheral circuit region to extend in the first direction; and
a plurality of second sub row decoders, spaced apart from one another in the second direction in a second row adjacent to the first row in the first direction to extend in the first direction,
wherein the plurality of first sub row decoders and the plurality of second sub row decoders are each arranged in a zigzag shape.
6. The storage device of claim 5 , wherein
the 3D memory cell array comprises a plurality of memory blocks,
the plurality of first sub row decoders are arranged at an equal interval, in groups of four, with respect to each of the plurality of memory blocks, and
the plurality of second sub row decoders are arranged at an equal interval, in groups of three, with respect to each of the plurality of memory blocks.
7. The storage device of claim 5 , wherein
the 3D memory cell array comprises a plurality of memory blocks,
the plurality of first sub row decoders are arranged at an equal interval, in groups of four, with respect to each of the plurality of memory blocks, and
the plurality of second sub row decoders are arranged at an equal interval, in groups of five, with respect to each of the plurality of memory blocks.
8. The storage device of claim 1 , wherein circuit devices operating on a low voltage are arranged in a region of the second peripheral circuit region.
9. The storage device of claim 8 , wherein
the second peripheral circuit region further comprises a scheduler configured to control at least one of a voltage level, an application timing, and an application time of each of corresponding control signals according to an operation mode of the non-volatile memory device.
10. The storage device of claim 1 , wherein circuit devices operating on a high voltage are arranged in a region of the first peripheral circuit region.
11. The storage device of claim 10 , wherein the first peripheral circuit region further comprises a voltage generator configured to generate voltages needed for performing operations of the non-volatile memory device.
12. The storage device of claim 1 , wherein the second peripheral circuit region further comprises at least one circuit of a memory controller configured to control the non-volatile memory device.
13. A non-volatile memory device including a three-dimensional (3D) memory cell array including a plurality of memory blocks, the non-volatile memory device comprising:
a first substrate including a first peripheral circuit region including a row decoder, the row decoder configured to select one word line from among a plurality of word lines of the 3D memory cell array, and circuit devices operating based on a high voltage; and
a second substrate including a second peripheral circuit region, including a page buffer unit, the page buffer unit configured to select at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region, wherein
the cell region is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate, and
the page buffer unit extends in a second direction that is normal to a first direction.
14. The non-volatile memory device of claim 13 , wherein the row decoder comprises a plurality of second sub row decoders spaced apart from one another in the second direction and extending in the first direction.
15. The non-volatile memory device of claim 14 , wherein the plurality of second sub row decoders are arranged at an equal interval, in groups of five, with respect to each of the plurality of memory blocks.
16. The non-volatile memory device of claim 13 , wherein the row decoder comprises:
a plurality of first sub row decoders spaced apart from one another in the second direction in a first row of the first peripheral circuit region and extending in the first direction; and
a plurality of second sub row decoders spaced apart from one another in the second direction in a second row adjacent to the first row in the first direction and extending in the first direction,
wherein the plurality of first sub row decoders and the plurality of second sub row decoders are each arranged in a zigzag shape.
17. The non-volatile memory device of claim 16 , wherein
the plurality of first sub row decoders are arranged at an equal interval, in even numbered groups, with respect to each of the plurality of memory blocks, and
the plurality of second sub row decoders are arranged at an equal interval, in odd numbered groups, with respect to each of the plurality of memory blocks.
18. The non-volatile memory device of claim 13 , wherein the second peripheral circuit region further comprises a scheduler configured to control a voltage level, an application timing, and/or an application time of each of corresponding control signals according to an operation mode of the non-volatile memory device.
19. The non-volatile memory device of claim 13 , wherein the first peripheral circuit region further comprises a voltage generator configured to generate voltages needed for performing operations of the non-volatile memory device.
20. A method of manufacturing a storage device including a three-dimensional (3D) memory cell array, the method comprising:
forming a first peripheral circuit region, including a row decoder, the row decoder configured to select one word line from among a plurality of word lines of the 3D memory cell array, and circuit devices operating on a high voltage, in a first substrate;
forming a second peripheral circuit region, including a page buffer unit, the page buffer unit configured to select at least one bit line from among a plurality of bit lines of the 3D memory cell array, and circuit devices operating on a low voltage, in a second substrate which differs from the first substrate;
forming a cell region, including the 3D memory cell array, on the second peripheral circuit region in the second substrate; and
vertically stacking the second substrate on the first substrate and bonding the second substrate to the first substrate so that the cell region is provided between the first peripheral circuit region and the second peripheral circuit region.