Vertical memory device with a double word line structure
A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.
1. A memory device comprising:
a substrate;
a vertical conductive line oriented vertically over the substrate;
an active layer oriented laterally from the vertical conductive line;
a pair of line-shaped conductive lines disposed over the active layer;
a first node electrically connected to the active layer;
a second node over the first node; and
a dielectric material disposed between the first node and the second node,
wherein the pair of line-shaped conductive lines comprises:
a line-shaped lower conductive line disposed over a lower surface of the active layer; and
a line-shaped upper conductive line disposed over an upper surface of the active layer,
wherein the active layer includes:
a first source/drain region coupled to the vertical conductive line;
a second source/drain region coupled to the first node; and
a channel between the first source/drain region and a second source/drain region, and
the first source/drain region, the channel, and the second source/drain region are positioned in a lateral arrangement parallel to the substrate.
2. The memory device of claim 1 , wherein the pair of line-shaped conductive lines are vertically stacked with the channel therebetween.
3. The memory device of claim 1 , further comprising:
a gate dielectric layer which is formed between the pair of line-shaped conductive lines and the channel.
4. The memory device of claim 1 , wherein the lower and upper line-shaped conductive lines are set to the same potential and are electrically connected to each other.
5. The memory device of claim 1 , wherein the first node has a lateral cylindrical shape, and
the second node includes:
an inner second node extending into a cylindrical shape of the first node; and
a plurality of outer second nodes surrounding an outside of the cylindrical shape of the first node.