Method of operating an integrated circuit and integrated circuit
View Patent ↗An integrated circuit includes a first memory cell array and a controller. The first memory cell array includes a first array of volatile memory cells having a first retention data time. The controller is coupled to the first memory cell array. The controller is configured to write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into, read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on, and determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.
1. An integrated circuit, comprising:
a first memory cell array comprising:
a first array of volatile memory cells having a first retention data time; and
a controller coupled to the first memory cell array, the controller being configured to:
write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into;
read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on; and
determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.
2. The integrated circuit of claim 1 , wherein the controller being configured to write data to each memory cell in the first memory cell array comprises:
the controller being configured to write a logic 1 to each memory cell in the first memory cell array.
3. The integrated circuit of claim 1 , wherein the controller being configured to determine whether to allow the authentication operation of the integrated circuit comprises:
the controller being configured to determine data read from at least one memory cell in the first memory cell array is not equal to data written to the at least one memory cell in the first memory cell array.
4. The integrated circuit of claim 3 , wherein the controller being configured to determine whether to allow the authentication operation of the integrated circuit further comprises the controller being further configured to:
determine a first time since powering off the integrated circuit is greater than a minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;
set a flag to a first value in response to the controller being configured to determine the first time since powering off the integrated circuit is greater than the minimum time; and
allow an authentication operation of the integrated circuit in response to the flag being the first value.
5. The integrated circuit of claim 4 , wherein the controller being configured to determine whether to allow the authentication operation of the integrated circuit comprises:
the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array.
6. The integrated circuit of claim 5 , wherein the controller being configured to determine whether to allow the authentication operation of the integrated circuit further comprises the controller being further configured to:
determine the first time since powering off the integrated circuit is not greater than the minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array;
set the flag to a second value in response to the controller being configured to determine the first time since powering off the integrated circuit is not greater than the minimum time, the second value being different from the first value; and
not allow the authentication operation of the integrated circuit in response to the flag being the second value.
7. The integrated circuit of claim 1 , wherein
the integrated circuit is powered off, and the integrated circuit is powered on after being powered off;
the controller configured to read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on comprises:
the controller being further configured to read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on after being powered off; and
the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array comprises:
the controller being further configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array after the integrated circuit is powered on after being powered off.
8. An integrated circuit, comprising:
a first memory cell array comprising:
a first array of volatile memory cells having a first retention data time;
a controller coupled to the first memory cell array, the controller being configured to:
write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into;
read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on; and
determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array;
a second memory cell array coupled to the controller, the second memory cell array comprising:
a second array of volatile memory cells having a second retention data time different from the first retention data time, a first size of the first memory cell array is different from a second size of the second memory cell array.
9. The integrated circuit of claim 8 , wherein the controller is further configured to:
write data to each memory cell in the second memory cell array in response to the integrated circuit being successfully logged into;
read data from each memory cell in the second memory cell array in response to the integrated circuit being powered on; and
determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the second memory cell array.
10. The integrated circuit of claim 9 , wherein the controller configured to:
write data to each memory cell in the first memory cell array comprises:
the controller being configured to write a logic 1 to each memory cell in the first memory cell array; and
write data to each memory cell in the second memory cell array comprises:
the controller being configured to write the logic 1 to each memory cell in the second memory cell array.
11. The integrated circuit of claim 9 , wherein the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array comprises:
the controller being configured to determine whether data read from at least one memory cell in the first memory cell array is equal to data written to the at least one memory cell in the first memory cell array.
12. The integrated circuit of claim 11 , wherein the controller configured to determine whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises:
the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array.
13. The integrated circuit of claim 12 , wherein the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array further comprises the controller being configured to:
determine a first time since powering off the integrated circuit is not greater than a minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array;
set a first flag to a first value in response to the controller being configured to determine the first time since powering off the integrated circuit is not greater than the minimum time;
not allow the authentication operation of the integrated circuit in response to the first flag being the first value;
wait until the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;
determine the first time since powering off the integrated circuit is greater than the minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;
set the first flag to a second value in response to the controller being configured to determine the first time since powering off the integrated circuit is greater than the minimum time, the second value being different from the first value; and
allow the authentication operation of the integrated circuit in response to the first flag being the second value.
14. The integrated circuit of claim 11 , wherein the controller configured to determine whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises:
the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array.
15. The integrated circuit of claim 14 , wherein the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array comprises:
the controller being configured to determine whether data read from at least one memory cell in the second memory cell array is equal to data written to the at least one memory cell in the second memory cell array in response to the controller being configured to determine the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array.
16. The integrated circuit of claim 15 , wherein the controller configured to determine whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises:
the controller being configured to determine the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array.
17. The integrated circuit of claim 16 , wherein the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises the controller being configured to:
determine a first time since powering off the integrated circuit is greater than a minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array;
set a first flag to a first value in response to the controller being configured to determine the first time since powering off the integrated circuit is greater than the minimum time; and
allow the authentication operation of the integrated circuit in response to the first flag being the first value.
18. The integrated circuit of claim 17 , wherein the controller configured to determine whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises:
the controller being configured to determine the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array.
19. The integrated circuit of claim 18 , wherein the controller configured to determine whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises the controller being configured to:
determine the first time since powering off the integrated circuit is not greater than the minimum time in response to the controller being configured to determine the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array;
set the first flag to a second value in response to the controller being configured to determine the first time since powering off the integrated circuit is not greater than the minimum time, the second value being different from the first value; and
not allow the authentication operation of the integrated circuit in response to the first flag being the second value.
20. An integrated circuit, comprising:
a first memory cell array comprising:
a first array of volatile memory cells having a first retention data time; and
a controller coupled to the first memory cell array, the controller being configured to:
write a logic 1 as data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into;
read data from each memory cell in the first memory cell array in response to the integrated circuit being connected to a supply voltage after being disconnected from the supply voltage; and
determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array and after the integrated circuit is connected to the supply voltage after being disconnected from the supply voltage.