Backside contact structures with stacked metal silicide layers for source/drain region of fin field transistors

1. A method, comprising:

forming a semiconductor device on a first side of a substrate, wherein the semiconductor device comprises a source/drain (S/D) region;

etching a portion of the S/D region on a second side of the substrate to form an opening, wherein the second side is opposite to the first side; and

forming an epitaxial contact structure on the S/D region in the opening, wherein the epitaxial contact structure comprises a first portion in contact with the S/D region in the opening and a second portion on the first portion, a width of the second portion being larger than the first portion.

2. The method of claim 1 , wherein the forming the epitaxial contact structure comprises forming the second portion having a rounded surface.

3. The method of claim 1 , wherein the forming the epitaxial contact structure comprises forming the second portion having one or more facets.

4. The method of claim 1 , wherein a ratio of the width of the second portion to the width of the first portion ranges from about 1.1 to about 3.

5. The method of claim 1 , wherein the forming the epitaxial contact structure comprises forming the epitaxial contact structure at a temperature ranging from about 350° C. to about 450° C.

6. The method of claim 1 , wherein the forming the epitaxial contact structure comprises epitaxially growing the epitaxial contact structure with an active dopant at a concentration higher than about 1×10 21 cm −3 .

7. The method of claim 1 , further comprising:

forming an additional semiconductor device on the first side of the substrate, wherein the additional semiconductor device comprises an additional S/D region with a different type of dopant from the S/D region;

etching a portion of the additional S/D region on the second side of the substrate to form an additional opening; and

blocking the additional S/D region in the additional opening while forming the epitaxial contact structure on the S/D region.

8. The method of claim 7 , wherein blocking the additional S/D region comprises:

forming a mask layer in the additional opening before forming the epitaxial contact structure; and

removing the mask layer in the additional opening after forming the epitaxial contact structure.

9. The method of claim 7 , further comprising:

forming a barrier layer in the additional opening;

forming a metal silicide layer on the epitaxial contact structure and the additional S/D region; and

forming a metal contact on the metal silicide layer.

10. The method of claim 7 , further comprising:

selectively forming a first metal silicide layer on the epitaxial contact structure;

forming a second metal silicide layer on the first metal silicide layer and the additional S/D region, wherein the second metal silicide layer comprises a metal different from the first metal silicide layer; and

forming a metal contact on the second metal silicide layer.

11. The method of claim 1 , further comprising:

forming a first power rail structure on the first side of the substrate and connected to a gate structure of the semiconductor device; and

forming a second power rail structure on the second side of the substrate and connected to the S/D region of the semiconductor device.

12. A method, comprising:

forming first and second semiconductor devices on a first side of a substrate, wherein the first semiconductor device comprises a first source/drain (S/D) region and the second semiconductor device comprises a second S/D region;

etching, on a second side of the substrate, a portion of the first S/D region to form a first opening and a portion of the second S/D region to form a second opening, wherein the second side is opposite to the first side;

selectively forming a first metal silicide layer on the second S/D region in the second opening; and

forming a second metal silicide layer on the first metal silicide layer and on the first S/D region, wherein the second metal silicide layer comprises a metal different from the first metal silicide layer.

13. The method of claim 12 , further comprising:

forming a barrier layer in the first and second openings before selectively forming the first metal silicide layer;

forming a metal contact on the second metal silicide layer; and

forming a power rail structure on the second metal silicide layer.

14. The method of claim 13 , wherein the forming the barrier layer comprises:

depositing a conformal barrier layer in the first and second openings;

etching a portion of the conformal barrier layer in contact with the first and second S/D regions.

15. The method of claim 12 , wherein the selectively forming the first metal silicide layer comprises forming the first metal silicide layer at a temperature below about 450° C.

16. The method of claim 12 , wherein the selectively forming the first metal silicide layer comprises forming the first metal silicide layer with a metal precursor including at least one of nickel, cobalt, and ruthenium.

17. A semiconductor device, comprising:

a stack of semiconductor layers on a first side of a substrate;

a gate structure wrapped around the stack of semiconductor layers;

a source/drain (S/D) region in contact with the stack of semiconductor layers;

an inner spacer structure between the stack of semiconductor layers; and

an epitaxial contact structure comprising a semiconductor material and in contact with the S/D region on a second side of the substrate, wherein:

the epitaxial contact structure comprises a first portion in contact with the S/D region and the inner spacer structure and a second portion above the first portion;

a width of the second portion is larger than a width of the first portion; and

the second side is opposite to the first side.

18. The semiconductor structure of claim 17 , further comprising a first metal silicide layer in contact with the epitaxial contact structure and a second metal silicide layer on the first metal silicide layer, wherein the second metal silicide layer comprises a metal different from the first metal silicide layer.

19. The semiconductor structure of claim 17 , further comprising an interlayer dielectric (ILD) layer on the gate structure, wherein the first portion of the epitaxial contact structure is in contact with the ILD layer and the second portion of the epitaxial contact structure is above the ILD layer.

20. The semiconductor structure of claim 17 , wherein a ratio of the width of the second portion to the width of the first portion ranges from about 1.1 to about 3.