Level shifting circuit manufacturing method

1. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming first through fourth PMOS transistors in an n-well;

constructing a bias circuit comprising the first and second PMOS transistors;

constructing a level shifter comprising the third and fourth PMOS transistors;

building a first power distribution structure comprising electrical connections to each of the first and third PMOS transistors; and

building a second power distribution structure comprising electrical connections to each of the second and fourth PMOS transistors.

2. The method of claim 1 , wherein the constructing the bias circuit comprises electrically coupling the n-well to a first source/drain (S/D) terminal of each of the first and second PMOS transistors.

3. The method of claim 2 , wherein

the building the first power distribution structure comprises electrically connecting the first power distribution structure to a second S/D terminal of the first PMOS transistor and to a gate of the second PMOS transistor, and

the building the second power distribution structure comprises electrically connecting the second power distribution structure to a second S/D terminal of the second PMOS transistor and to a gate of the first PMOS transistor.

4. The method of claim 2 , wherein

the forming the first through fourth PMOS transistors in the n-well comprises forming a fifth PMOS transistor in the n-well,

the constructing the bias circuit comprises:

constructing the bias circuit comprising the fifth PMOS transistor coupled in series with an NMOS transistor; and

electrically connecting a gate of the second PMOS transistor to a node between the fifth PMOS transistor and the NMOS transistor,

the building the first power distribution structure comprises electrically connecting the first power distribution structure to a second S/D terminal of the first PMOS transistor and to a first S/D terminal of the fifth PMOS transistor, and

the building the second power distribution structure comprises electrically connecting the second power distribution structure to a second S/D terminal of the second PMOS transistor, a gate of the first PMOS transistor, and a gate of the fifth PMOS transistor.

5. The method of claim 1 , wherein

the forming the first through fourth PMOS transistors in the n-well comprises forming a fifth PMOS transistor in the n-well, and

the constructing the level shifter comprises constructing the level shifter comprising the fifth PMOS transistor.

6. The method of claim 1 , wherein the forming the first through fourth PMOS transistors in the n-well comprises forming an NMOS transistor outside the n-well.

7. The method of claim 6 , wherein one of the building the first power distribution structure or the building the second power distribution structure comprises forming an electrical connection from a source/drain terminal and a bulk terminal of the NMOS transistor to a reference node configured to have a reference voltage.

8. The method of claim 1 , wherein the forming the first through fourth PMOS transistors in the n-well comprises forming each of the first through fourth PMOS transistors comprising a bulk terminal electrically connected to the n-well.

9. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming first through fourth PMOS transistors in an n-well;

constructing a bias circuit comprising the first and second PMOS transistors;

constructing a level shifter comprising the third and fourth PMOS transistors;

building a first power distribution structure comprising electrical connections to a first source/drain (S/D) terminal of each of the first and third PMOS transistors; and

building a second power distribution structure comprising electrical connections to a first S/D terminal of each of the second and fourth PMOS transistors.

10. The method of claim 9 , wherein the constructing the bias circuit comprises forming an electrical connection from a second S/D terminal of each of the first and second PMOS transistors to the n-well.

11. The method of claim 10 , wherein

the building the first power distribution structure comprises forming an electrical connection to a gate of the second PMOS transistor, and

the building the second power distribution structure comprises forming an electrical connection to a gate of the first PMOS transistor.

12. The method of claim 10 , wherein

the forming the first through fourth PMOS transistors in the n-well comprises forming a fifth PMOS transistor in the n-well;

the constructing the bias circuit comprises constructing the bias circuit comprising the fifth PMOS transistor comprising a first S/D terminal electrically connected to a gate of the first PMOS transistor,

the building the first power distribution structure comprises forming an electrical connection to a second S/D terminal of the fifth PMOS transistor, and

the building the second power distribution structure comprises forming an electrical connection to a gate of the fifth PMOS transistor.

13. The method of claim 12 , wherein the constructing the bias circuit further comprises constructing the bias circuit comprising the fifth PMOS transistor comprising the first S/D terminal electrically connected to a S/D terminal of an NMOS transistor.

14. The method of claim 9 , wherein

the building the first power distribution structure comprises forming the electrical connections from the first terminal of each of the first and third PMOS transistors to a first power supply node of a first power domain, and

the building the second power distribution structure comprises forming the electrical connections from the first terminal of each of the second and fourth PMOS transistors to a second power supply node of a second power domain independent from the first power domain.

15. The method of claim 14 , wherein

the first power supply node is configured to have a first power supply voltage, and

the second power supply node is configured to have a second power supply voltage greater than the first power supply voltage.

16. The method of claim 15 , wherein

the second power supply node is configured to have the second power supply voltage greater than the first power supply voltage by a difference less than a threshold voltage of the first through fourth PMOS transistors.

17. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming an n-well in a semiconductor substrate;

forming first through fifth PMOS transistors in the n-well;

constructing a bias circuit comprising the first and second PMOS transistors;

constructing a level shifter comprising the third through fifth PMOS transistors;

building a first power distribution structure comprising electrical connections to each of the first and third PMOS transistors; and

building a second power distribution structure comprising electrical connections to each of the second, fourth, and fifth PMOS transistors.

18. The method of claim 17 , wherein the forming the n-well in the semiconductor substrate comprises forming the n-well in an epitaxial layer of the semiconductor substrate.

19. The method of claim 18 , wherein

the forming the n-well in the semiconductor substrate comprises forming a plurality of n-wells in the semiconductor substrate,

the forming the first through fifth PMOS transistors in the n-well comprises forming the first through fifth PMOS transistors in the plurality of n-wells, and

the constructing the bias circuit comprises constructing the bias circuit configured to bias each n-well of the plurality of n-wells.

20. The method of claim 17 , wherein the constructing the bias circuit comprises forming an electrical connection from a source/drain (S/D) terminal of each of the first and second PMOS transistors to the n-well.