IP Library › Granted Patent US 12,154,827
Granted Patent B2
US 12,154,827 · App. 18/383,086 · Granted Nov 26, 2024

Semiconductor device having plurality of insulators

Inventors: Shunpei Yamazaki (Tokyo, JP); Toshihiko Takeuchi (Kanagawa, JP); Tsutomu Murakawa (Kanagawa, JP); Hiroki Komagata (Kanagawa, JP); Daisuke Matsubayashi (Kanagawa, JP); Noritaka Ishihara (Kanagawa, JP); Yusuke Nonaka (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L21/8234H01L27/06H01L27/088H01L29/7869H10B12/00
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Quick Facts
Patent No.
US 12,154,827
App. No.
18/383,086
Granted
Nov 26, 2024
Kind
B2
Abstract

A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.

Claims (23)

1. A semiconductor device comprising:

a first insulator;

an oxide semiconductor layer over the first insulator;

a second insulator comprising an opening over the oxide semiconductor layer;

a gate insulating film over the oxide semiconductor layer;

a gate electrode over the gate insulating film;

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

wherein the first insulator and the second insulator comprise silicon oxide,

wherein the gate insulating film and the gate electrode are in the opening,

wherein the second insulator is in contact with the first insulator, and

wherein a top surface of the second insulator and a top surface of the gate electrode are coplanar.

2. A semiconductor device comprising:

a first insulator;

an oxide semiconductor layer over the first insulator;

a second insulator over the oxide semiconductor layer;

a third insulator comprising an opening over the oxide semiconductor layer;

a gate insulating film over the oxide semiconductor layer;

a gate electrode over the gate insulating film;

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

wherein the first insulator and the third insulator comprise silicon oxide,

wherein the gate insulating film and the gate electrode are in the opening,

wherein the third insulator is in contact with the first insulator, and

wherein the second insulator is in contact with a side surface of the gate insulating film and a side surface of the gate electrode in the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2023
From: YAMAZAKI, SHUNPEI; TAKEUCHI, TOSHIHIKO; MURAKAWA, TSUTOMU; KOMAGATA, HIROKI; MATSUBAYASHI, DAISUKE; ISHIHARA, NORITAKA; NONAKA, YUSUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 065319/0662 →
Priority Claims (3)
JP 2017-170022 · Sep 5, 2017 · national
JP 2017-170023 · Sep 5, 2017 · national
JP 2017-238210 · Dec 13, 2017 · national
Continuity (3)
Continuation 17518614 · Nov 4, 2021
Continuation 16643195
Related Publication 20240055299A1 · Feb 15, 2024
Cited By (1)
US 12,563,755