IP Library Granted Patent US 12,563,755
Granted Patent B2
US 12,563,755 · App. 18/022,304 · Granted Feb 24, 2026

Semiconductor device and manufacturing method thereof

Inventors: Shunpei Yamazaki (Tokyo, JP); Sachiaki Tezuka (Atsugi, JP); Haruyuki Baba (Isehara, JP); Yuji Egi (Atsugi, JP); Yasuhiro Jinbo (Isehara, JP); Yujiro Sakurada (Atsugi, JP); Takeshi Aoki (Ebina, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D1/692H01L21/3115
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,563,755
App. No.
18/022,304
Granted
Feb 24, 2026
Kind
B2
Abstract

A semiconductor device with a small variation in characteristics is provided. In a manufacturing method of a semiconductor device including a capacitor with reduced leak current, a first conductor is formed; a second insulator is formed over the first conductor; a third insulator is formed over the second insulator; a second conductor is formed over the third insulator; a fourth insulator is deposited over the second conductor and the third insulator; by heat treatment, hydrogen contained in the third insulator diffuses into or is absorbed by the second insulator; the first conductor is one electrode of the capacitor; the second conductor is the other electrode of the capacitor; and each of the second insulator and the third insulator is a dielectric of the capacitor.

Claims (40)

1 . A manufacturing method of a semiconductor device comprising a capacitor whose leak current is lower than or equal to 1.5×10 −21 (A) per capacitance of 4.3 fF in a measurement environment at a temperature of 125° C., the method comprising the steps of:

forming a first conductor;

forming a second insulator over the first conductor;

forming a third insulator over the second insulator;

performing microwave treatment over the third insulator;

forming a second conductor over the third insulator; and

depositing a fourth insulator over the second conductor and the third insulator,

wherein, by heat treatment, hydrogen contained in the third insulator diffuses into and is absorbed by the second insulator,

wherein the first conductor is one electrode of the capacitor,

wherein the second conductor is the other electrode of the capacitor, and

wherein each of the second insulator and the third insulator is a dielectric of the capacitor.

2 . The manufacturing method of a semiconductor device according to claim 1 ,

wherein the second insulator is a metal oxide deposited by an ALD method and containing aluminum, and

wherein the third insulator is an oxide deposited by a CVD method and containing silicon and nitrogen.

3 . A manufacturing method of a semiconductor device comprising a capacitor whose leak current is lower than or equal to 1.5×10 −21 (A) per capacitance of 4.3 fF in a measurement environment at a temperature of 125° C., the method comprising the steps of:

forming a first conductor;

forming a second insulator over the first conductor;

performing microwave treatment over the second insulator;

forming a third insulator over the second insulator;

forming a second conductor over the third insulator; and

depositing a fourth insulator over the second conductor and the third insulator,

wherein, by heat treatment, hydrogen contained in the second insulator diffuses into and is absorbed by the third insulator,

wherein the first conductor is one electrode of the capacitor,

wherein the second conductor is the other electrode of the capacitor, and

wherein each of the second insulator and the third insulator is a dielectric of the capacitor.

4 . The manufacturing method of a semiconductor device according to claim 3 ,

wherein the second insulator is an oxide deposited by a CVD method and containing silicon and nitrogen, and

wherein the third insulator is a metal oxide deposited by an ALD method and containing aluminum.

5 . The manufacturing method of a semiconductor device according to claim 1 ,

wherein the microwave treatment is performed using a gas containing oxygen, and

wherein a pressure of the microwave treatment is lower than or equal to 133 Pa.

6 . The manufacturing method of a semiconductor device according to claim 3 ,

wherein the microwave treatment is performed using a gas containing oxygen, and

wherein a pressure of the microwave treatment is lower than or equal to 133 Pa.

7 . The manufacturing method of a semiconductor device according to claim 1 ,

wherein a temperature of the heat treatment is higher than or equal to 300° C. and lower than or equal to 550° C., and

wherein time for the heat treatment is longer than or equal to 2 hours and shorter than or equal to 16 hours.

8 . The manufacturing method of a semiconductor device according to claim 3 ,

wherein a temperature of the heat treatment is higher than or equal to 300° C. and lower than or equal to 550° C., and

wherein time for the heat treatment is longer than or equal to 2 hours and shorter than or equal to 16 hours.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2023
From: YAMAZAKI, SHUNPEI; TEZUKA, SACHIAKI; BABA, HARUYUKI; EGI, YUJI; JINBO, YASUHIRO; SAKURADA, YUJIRO; AOKI, TAKESHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 062751/0875 →
Priority Claims (1)
JP 2020-143496 · Aug 27, 2020 · national
Continuity (1)
Related Publication 20230326955A1 · Oct 12, 2023
References Cited (40)
US 8084370B2 · Forbes · 2011 [cited by examiner]
US 8455868B2 · Yamazaki et al. · 2013 [cited by applicant]
US 8547771B2 · Koyama · 2013 [cited by applicant]
US 8902637B2 · Takemura · 2014 [cited by applicant]
US 8995174B2 · Koyama · 2015 [cited by applicant]
US 9349735B2 · Yamazaki et al. · 2016 [cited by applicant]
US 9991265B2 · Yamazaki et al. · 2018 [cited by applicant]
US 10553589B2 · Yamazaki et al. · 2020 [cited by applicant]
US 11177792B2 · Koyama · 2021 [cited by applicant]
US 11195758B2 · Yamazaki et al. · 2021 [cited by applicant]
US 11289475B2 · Yamazaki et al. · 2022 [cited by applicant]
US 11456296B2 · Yamazaki et al. · 2022 [cited by applicant]
US 11804407B2 · Yamazaki et al. · 2023 [cited by applicant]
US 12154827B2 · Yamazaki et al. · 2024 [cited by applicant]
US 20050142715A1 · Sakoda · 2005 [cited by examiner]
US 20070085154A1 · Murakawa · 2007 [cited by examiner]
US 20120113707A1 · Takemura · 2012 [cited by applicant]
US 20150078066A1 · Takemura · 2015 [cited by applicant]
US 20150280691A1 · Koyama · 2015 [cited by applicant]
US 20200135445A1 · Yamazaki et al. · 2020 [cited by applicant]
US 20210328580A1 · Koyama · 2021 [cited by applicant]
US 20220199613A1 · Yamazaki et al. · 2022 [cited by applicant]
US 20220271168A1 · Yamazaki et al. · 2022 [cited by applicant]
CN 102543174A · 2012 [cited by applicant]
CN 110506325A · 2019 [cited by applicant]
JP 2005184024A · 2005 [cited by applicant]
JP 2011151383A · 2011 [cited by applicant]
JP 2012119050A · 2012 [cited by applicant]
JP 2012257187A · 2012 [cited by applicant]
JP 2017084440A · 2017 [cited by applicant]
JP 2017204647A · 2017 [cited by applicant]
JP 2020120116A · 2020 [cited by applicant]
JP 2020123612A · 2020 [cited by applicant]
KR 20190142334A · 2019 [cited by applicant]
WO WO2018197988 · 2018 [cited by applicant]
WO WO2019048983 · 2019 [cited by applicant]
Ishizu.T et al., “A 140 MHz 1 Mbit 2T1C Gain-Cell Memory with 60-nm Indium-Gallium-Zinc Oxide Transistor Embedded into 65-nm CMOS Logic Process Technology”, 2017 Symposium on VLSI Circuits Digest of Technical Papers, Ju… [cited by applicant]
Yamazaki.S et al., “Crystalline IGZO ceramics (crystalline oxide semiconductor)-based devices for artificial intelligence”, International Journal of Ceramic Engineering & Science(IJCES), Mar. 22, 2019, vol. 1, No. 1, pp… [cited by applicant]
International Search Report (Application No. PCT/IB2021/057428), dated Oct. 26, 2021. [cited by applicant]
Written Opinion (Application No. PCT/IB2021/057428), dated Oct. 26, 2021. [cited by applicant]