Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

1. A semiconductor packaging method, comprising:

forming a first stage assembly, including:

providing at least one first-stage device, at least one second-stage device, a carrier board, and a clamping board, wherein each of the at least one first-stage device respectively has a first-stage first surface and an opposing first-stage second surface, the first-stage first surface is formed with first-stage interconnect pads, the first-stage second surface is formed with first-stage first alignment solder parts, each of the at least one second-stage device respectively has a second-stage first surface, the second-stage first surface is formed with second-stage interconnect terminals and second-stage first alignment solder parts, and the carrier board is formed with first-stage second alignment solder parts respectively corresponding to the first-stage first alignment solder parts, and wherein at least one of the carrier board and the clamping board has at least one opening;

placing the at least one first-stage device on the carrier board such that the first alignment solder parts are substantially aligned with respective ones of the second alignment solder parts;

forming alignment solder joints by soldering the first alignment solder parts to respective ones of the second alignment solder parts to align and fix the at least one first-stage device to the carrier board;

injecting a molding compound through the at least one opening to form a molded package body encapsulating the at least one first-stage device between the carrier board and the clamping board, the clamping board abutting the first-stage first surface of each of the at least one first-stage device;

removing the clamping board to expose the first-stage first surface of each of the at least one first-stage device;

sequentially forming an interconnect layer and interposer terminals on a side of the molded package body where the first-stage first surface of each of the at least one first-stage device is exposed, the interposer terminals including respective terminals corresponding to the second-stage interconnect terminals on a respective second-stage device of the at least one second-stage device, wherein at least some of the first-stage interconnect pads of each of the at least one first-stage device are respectively electrically connected to at least some of the interposer terminals, through the interconnect layer; and

forming second-stage second alignment solder parts corresponding to the second-stage first alignment solder parts, respectively, on the interconnect layer;

placing the at least one second-stage device over the interconnect layer such that the second-stage first alignment solder parts are substantially aligned with the second-stage second alignment solder parts;

forming second-stage alignment solder joints by soldering the second-stage first alignment solder parts and the second-stage second alignment solder parts so that the at least one second-stage device is precisely aligned to the first-stage assembly;

pressing the at least one second-stage device and the first-stage assembly toward each other while the second-stage alignment solder joints are at least partially melted to respectively join the second-stage interconnection terminals and the interposer terminals to form interconnect joints; and

releasing the pressing.

2. The semiconductor packaging method according to claim 1 , wherein the at least one first-stage device and the at least one second-stage device includes at least one of a semiconductor device and an interconnect board, the interconnect board being an interposer or a substrate.

3. The semiconductor packaging method according to claim 1 , wherein at least one of the at least one first-stage device and the at least one second-stage device further includes a through electrode.

4. The semiconductor packaging method according to claim 1 , wherein a sum of heights of a second-stage interconnect terminal and a corresponding interposer terminal is less than a sum of heights of a second-stage first alignment solder part and a corresponding second-stage second alignment solder part, such that the second-stage interconnect terminals are spaced apart from the interposer terminals after the second-stage first alignment solder parts and the second-stage second alignment solder parts form second-stage alignment solder joints.

5. The semiconductor packaging method according to claim 1 , further comprising forming external interconnect terminals on the interconnect layer such that at least some of the first-stage interconnect pads are respectively electrically connected to the external interconnect terminals through the interconnect layer.

6. The semiconductor packaging method according to claim 1 , wherein respectively joining the second-stage interconnection terminals and the interposer terminals to form interconnect joints includes, while the at least one second-stage device is in precise alignment with the first-stage assembly and the second-stage alignment solder joints are still in an at least partially molten state, pressing the at least one second-stage device and the first-stage assembly toward each other.

7. The semiconductor packaging method according to claim 6 , wherein the plurality of external interconnect terminals are spaced apart from the second level second alignment solder parts so as not to be covered by a perpendicular projection of the at least one second-stage device on the interconnect layer after at least one second-stage device is precisely aligned with the first-stage assembly.

8. The semiconductor packaging method according to claim 1 , wherein respectively joining the second-stage interconnection terminals and the interposer terminals to form interconnect joints includes, after the at least one second-stage device is in precise alignment with the first-stage assembly, applying heat to melt the second-stage alignment solder joints again and pressing the at least one second-stage device and the first-stage assembly toward each other when the second-stage alignment solder joints are in a molten or partially molten state.

9. The semiconductor packaging method according to claim 1 , wherein:

the second-stage interconnect terminals are interconnect bumps, and the interposer terminals are interposer bumps or interposer pads; or

the second-stage interconnect terminals are interconnect pads and the interposer terminals are interposer bumps.

10. The semiconductor packaging method according to claim 9 , wherein:

the interconnect bumps are solder bumps and respectively joining the second-stage interconnect terminals and the interposer terminals includes soldering the second-stage interconnect terminals to respective ones of the interposer terminals to form interconnect joints; or

the interconnect bumps does not include solder and respectively joining the second-stage interconnect terminals and the interposer terminals includes bonding the second-stage interconnect terminals and respective ones of the interposer terminals by thermocompression bonding.

11. A semiconductor packaging method, comprising:

forming a first stage assembly, including:

providing at least one first-stage device, at least one second-stage device, a carrier board, and a clamping board, wherein each of the at least one first-stage device respectively has a first-stage first surface and an opposing first-stage second surface, the first-stage first surface is formed with first-stage interconnect pads, the first-stage second surface is formed with first-stage first alignment solder parts, each of the at least one second-stage device respectively has a second-stage first surface, the second-stage first surface is formed with second-stage interconnect bumps and second-stage first alignment solder parts, the second-stage interconnect bumps respectively corresponding with at least some of the first-stage interconnect pads, and the carrier board is formed with first-stage second alignment solder parts respectively corresponding to the first-stage first alignment solder parts, and wherein at least one of the carrier board and the clamping board has at least one opening;

placing the at least one first-stage device on the carrier board such that the first alignment solder parts are substantially aligned with respective ones of the second alignment solder parts;

forming alignment solder joints by soldering the first alignment solder parts to respective ones of the second alignment solder parts to align and fix the at least one first-stage device to the carrier board;

injecting a molding compound through the at least one opening to form a molded package body encapsulating the at least one first-stage device between the carrier board and the clamping board, the clamping board attached to the first-stage first surface of each of the at least one first-stage device; and

removing the clamping board to expose the first-stage first surface of each of the at least one first-stage device;

placing the at least one second-stage device on the first-stage assembly such that the second-stage first alignment solder parts are substantially aligned with second-stage second alignment solder parts on the first-stage assembly, wherein the second-stage second alignment solder parts are pre-formed on a side of the first-stage assembly where the first-stage first surface is exposed and respectively correspond with the second-stage first alignment solder parts;

forming second-stage alignment solder joints by soldering the second-stage first alignment solder parts and the second-stage second alignment solder parts so that the at least one second-stage device is precisely aligned to the first-stage assembly;

pressing the at least one second-stage device and the first-stage assembly toward each other while the second-stage alignment solder joints are at least partially melted to respectively join the second-stage interconnection bumps and the corresponding first-stage interconnect pads to form interconnect joints; and

releasing the pressing.

12. The semiconductor packaging method according to claim 11 , wherein the at least one first-stage device and the at least one second-stage device includes at least one of a semiconductor device and an interconnect board, the interconnect board being a interposer or a substrate.

13. The semiconductor packaging method according to claim 11 , wherein at least one of the at least one first-stage device and the at least one second-stage device further includes a through electrode.

14. The semiconductor packaging method according to claim 11 , wherein a sum of heights of a second-stage interconnect terminal and a corresponding interposer terminal is less than a sum of heights of a second-stage first alignment solder part and a corresponding second-stage second alignment solder part, such that the second-stage interconnect terminals are spaced apart from the interposer terminals after the second-stage first alignment solder parts and the second-stage second alignment solder parts form second-stage alignment solder joints.

15. The semiconductor packaging method according to claim 11 , wherein pressing the at least one second-stage device and the first-stage assembly toward each other includes, while the at least one second-stage device is in precise alignment with the first-stage assembly and the second-stage alignment solder joints are still in an at least partially molten state, pressing the at least one second-stage device and the first-stage assembly toward each other.

16. The semiconductor packaging method according to claim 11 , wherein pressing the at least one second-stage device and the first-stage assembly toward each other includes, after the at least one second-stage device is in precise alignment with the first-stage assembly, applying heat to melt the second-stage alignment solder joints again and pressing the at least one second-stage device and the first-stage assembly toward each other when the second-stage alignment solder joints are in a molten or partially molten state.

17. The semiconductor packaging method according to claim 11 , wherein the second-stage interconnect bumps are respectively joined with the first stage interconnect pads by soldering the second-stage interconnect bumps to respective ones of the first-stage interconnect pad.

18. The semiconductor packaging method according to claim 11 , wherein the second-stage interconnect bumps are respectively joined with the first stage interconnect pads by thermocompression bonding.

19. The semiconductor packaging method of claim 11 , wherein the second-stage interconnect bumps and the second-stage first alignment solder parts together serve as second-stage interconnect terminals on the second-stage first surface of the at least one second-stage device, the second-stage interconnect terminals corresponding, respectively, with the first-stage interconnect pads on the at least one first-stage device.

20. The semiconductor packaging method of claim 11 , further comprising, after removing the clamping board and before placing the second-stage device on the first-stage assembly, forming the second-stage alignment solder parts on a side of the first-stage assembly where the first-stage first surface is exposed.