Profile of deep trench isolation structure for isolation of high-voltage devices
View Patent ↗In some embodiments, the present disclosure relates to a method that includes forming a shallow trench isolation (STI) structure that extends into a substrate. A masking layer is formed over the substrate and includes an opening overlying the STI structure. A first removal process removes portions of the STI structure underlying the opening of the STI structure. A second removal process laterally removes portions of the substrate below the STI structure. A third removal process removes portions of the substrate that directly underlie the opening of the masking layer. An insulator liner layer is formed within inner surfaces of the substrate as defined by the first, second, and third removal processes. Further, a fourth removal process removes portions of the insulator liner layer covering a lower surface of the substrate. A semiconductor material is then formed over the SOI substrate and on the insulator liner layer.
1. An integrated chip, comprising:
a substrate;
a shallow trench isolation (STI) structure extending into the substrate; and
a deep trench isolation (DTI) structure extending through the STI structure, wherein the DTI structure comprises a protrusion that protrudes laterally from a sidewall of the DTI structure to a location directly under the STI structure;
wherein the DTI structure comprises a semiconductor core structure directly contacting semiconductor material of the substrate at a bottom surface of the semiconductor core structure, and further comprises a dielectric liner structure laterally separating the semiconductor core structure from the substrate, and wherein the dielectric liner structure defines the protrusion.
2. The integrated chip according to claim 1 , wherein the protrusion directly contacts a bottom surface of the STI structure.
3. The integrated chip according to claim 1 , wherein the protrusion is closer to a bottom surface of the STI structure than to a bottom surface of the DTI structure.
4. The integrated chip according to claim 1 , wherein the protrusion coincides with a maximum width of the DTI structure.
5. The integrated chip according to claim 1 , wherein the DTI structure has a symmetrical cross-sectional profile.
6. The integrated chip according to claim 1 , wherein the substrate is a silicon-on-insulator (SOI) substrate, and wherein the DTI structure extends to an insulator layer of the SOI substrate.
7. An integrated chip, comprising:
a substrate;
a shallow trench isolation (STI) structure inset into a top surface of the substrate; and
a deep trench isolation (DTI) structure extending through the STI structure, wherein the DTI structure wraps around a bottom corner of the STI structure.
8. The integrated chip according to claim 7 , wherein the STI structure has an additional bottom corner on an opposite side of the DTI structure as the bottom corner, and wherein the DTI structure wraps around the additional bottom corner from a sidewall of the STI structure to a bottom surface of the STI structure.
9. The integrated chip according to claim 7 , wherein the DTI structure has a first width at a first elevation elevated relative to the bottom corner and further has a second width at a second elevation recessed relative to the bottom corner, and wherein the second width is greater than the first width.
10. The integrated chip according to claim 9 , wherein the first elevation is closer to the bottom corner than to the top surface of the substrate, and wherein the second elevation is closer to the bottom corner than to a bottom surface of the DTI structure.
11. The integrated chip according to claim 7 , wherein the DTI structure comprises a semiconductor core structure, and further comprises a dielectric liner structure localized to sidewalls of the semiconductor core structure and separating the sidewalls from the substrate.
12. The integrated chip according to claim 11 , wherein the semiconductor core structure directly contacts semiconductor material of the substrate at a bottom surface of the semiconductor core structure, and wherein the dielectric liner structure extends from the bottom surface of the semiconductor core structure to a top surface of the DTI structure and wraps around the bottom corner of the STI structure from a sidewall of the STI structure to a bottom surface of the STI structure.
13. The integrated chip according to claim 7 , further comprising:
a semiconductor device overlying and partially defined by the substrate, wherein the STI structure and the DTI structure extend in a closed path to surround and demarcate a device region of the substrate on which the semiconductor device is arranged.
14. An integrated chip, comprising:
a substrate;
a shallow trench isolation (STI) structure extending into a top of the substrate; and
a deep trench isolation (DTI) structure extending through the STI structure and comprising a semiconductor core structure and an insulator liner structure separating the semiconductor core structure from the STI structure and the substrate;
wherein a thickness of the insulator liner structure increases along a height of the DTI structure, towards the STI structure from a location recessed relative to a bottom surface of the STI structure, and wherein the thickness extends transverse to the height.
15. The integrated chip according to claim 14 , wherein the location is closer to the bottom surface of the STI structure than to a bottom surface of the DTI structure.
16. The integrated chip according to claim 14 , wherein the thickness of the insulator liner structure further increases along the height of the DTI structure, from a top surface of the STI structure to another location elevated relative to the bottom surface of the STI structure.
17. The integrated chip according to claim 14 , wherein a bottom surface of the semiconductor core structure is level with a bottom surface of the insulator liner structure.
18. The integrated chip according to claim 14 , wherein the insulator liner structure has a curved surface facing a width-wise center of the DTI structure and at a same elevation as the location.
19. The integrated chip according to claim 14 , wherein a width of the semiconductor core structure increases from a same elevation as the location to an elevation level with a top surface of the substrate.
20. The integrated chip according to claim 14 , wherein the STI structure separates a top portion of the DTI structure from the substrate.