Digital-to-analog converter (DAC) with adaptive calibration scheme
Methods and apparatus for controlling a power supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch; and calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells and having an output coupled to at least one of the plurality of DAC cells, the calibration circuitry being configured to sense a voltage of the first node in the first DAC cell and to control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on the sensed voltage of the first node.
1. A digital-to-analog converter (DAC) comprising:
a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch, wherein the current source is a cascoded current source comprising a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; and
calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells, having a second input coupled to the first DAC cell in the plurality of DAC cells, and having an output coupled to at least one of the plurality of DAC cells, the calibration circuity being configured to:
sense a voltage of the first node in the first DAC cell;
sense a voltage of the second node in the first DAC cell; and
control a power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on a voltage difference between the voltage of the first node and the voltage of the second node.
2. The DAC of claim 1 , wherein the calibration circuitry comprises a differential amplifier having a first input coupled to the first node in the first DAC cell and having a second input coupled to the second node in the first DAC cell.
3. The DAC of claim 2 , wherein the calibration circuitry further comprises a second switch coupled between the first node in the first DAC cell and the first input of the differential amplifier and a third switch coupled between the second node in the first DAC cell and the second input of the differential amplifier.
4. The DAC of claim 3 , wherein the second switch and the third switch comprise transmission gates.
5. The DAC of claim 3 , wherein the second switch and the third switch are configured to be in a closed state in response to receiving an indication that the DAC is in a calibration mode.
6. The DAC of claim 2 , wherein the calibration circuitry further comprises:
a comparator having a first input coupled to an output of the differential amplifier and having a second input coupled to a reference voltage source; and
logic having an input coupled to an output of the comparator.
7. The DAC of claim 6 , further comprising a voltage control module having an input coupled to an output of the logic, the voltage control module being configured to convert a signal at the output of the logic into the power supply voltage for the switch driver.
8. The DAC of claim 7 , wherein the voltage control module comprises another digital-to-analog converter (DAC).
9. The DAC of claim 1 , wherein the calibration circuitry is configured to increase the power supply voltage in response to determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage.
10. The DAC of claim 9 , wherein the calibration circuitry is configured to:
iteratively compare the reference voltage and the voltage difference between the voltage of the first node and the voltage of the second node; and
increase the power supply voltage until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.
11. The DAC of claim 9 , wherein the reference voltage is selected based on characteristics, including voltage and temperature variations, of at least one of:
the first transistor;
the second transistor; or
the calibration circuitry.
12. The DAC of claim 1 , wherein the power supply voltage is provided to a last stage of the switch driver in the at least one of the plurality of DAC cells.
13. A digital-to-analog converter (DAC) comprising:
a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch, wherein the current source is a cascoded current source comprising a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; and
calibration circuitry having a first input selectively coupled to a first DAC cell in the plurality of DAC cells and selectively coupled to a second DAC cell in the plurality of DAC cells, having a second input selectively coupled to the first DAC cell and selectively coupled to the second DAC cell, and having an output coupled to at least one of the plurality of DAC cells, the calibration circuity being configured to:
sense a voltage of the first node in the first DAC cell;
sense a voltage of the first node in the second DAC cell;
sense a voltage of the second node in the first DAC cell;
sense a voltage of the second node in the second DAC cell; and
control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on a first voltage difference between the voltage of the first node in the first DAC cell and the voltage of the second node in the first DAC cell and on a second voltage difference between the voltage of the first node in the second DAC cell and the voltage of the second node in the second DAC cell.
14. The DAC of claim 13 , wherein:
the calibration circuitry comprises a differential amplifier having a first input selectively coupled to the first node in the first DAC cell and selectively coupled to the first node in the second DAC cell and having a second input selectively coupled to the second node in the first DAC cell and selectively coupled to the second node in the second DAC cell;
the first DAC cell further comprises a second switch coupled between the first node in the first DAC cell and the first input of the differential amplifier and a third switch coupled between the second node in the first DAC cell and the second input of the differential amplifier; and
the second DAC cell further comprises a fourth switch coupled between the first node in the second DAC cell and the first input of the differential amplifier and a fifth switch coupled between the second node in the second DAC cell and the second input of the differential amplifier.
15. A wireless device comprising the DAC of claim 1 , the wireless device further comprising:
one or more antennas; and
one or more transmit paths coupled between one or more outputs of the DAC and the one or more antennas.
16. A method for operating a digital-to-analog converter (DAC) comprising a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch, wherein the current source is a cascoded current source comprising a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node, the method comprising:
sensing a voltage of the first node in a first DAC cell;
sensing a voltage of the second node in the first DAC cell; and
controlling a power supply voltage for the switch driver in at least one of the plurality of DAC cells, based on a voltage difference between the voltage of the first node and the voltage of the second node.
17. The method of claim 16 , further comprising:
determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage; and
increasing the power supply voltage in response to the determination.
18. The method of claim 16 , further comprising:
iteratively comparing a reference voltage and the voltage difference between the voltage of the first node and the voltage of the second node; and
increasing the power supply voltage until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.
19. The method of claim 16 , further comprising amplifying the voltage difference between the first node and the second node with a differential amplifier.
20. The method of claim 19 , wherein the sensing comprises:
closing a second switch coupled between the first node in the first DAC cell and a first input of the differential amplifier; and
closing a third switch coupled between the second node in the first DAC cell and a second input of the differential amplifier.
21. The method of claim 19 , further comprising:
comparing the amplified voltage difference and a reference voltage; and
outputting a digital logic signal based on the comparison, wherein the controlling comprises controlling the power supply voltage for the switch driver based on the digital logic signal.
22. The method of claim 16 , further comprising sensing a voltage of the first node in a second DAC cell, wherein the controlling comprises controlling the power supply voltage for the switch driver in the at least one of the plurality of DAC cells based on the sensed voltage of the first node in the first DAC cell and on the sensed voltage of the first node in the second DAC cell.
23. The method of claim 22 , wherein:
the current source is a cascoded current source comprising a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node;
the method further comprises sensing a voltage of the second node in the first DAC cell and a voltage of the second node in the second DAC cell; and
the controlling comprises controlling the power supply voltage for the switch driver based on a first voltage difference between the voltage of the first node in the first DAC cell and the voltage of the second node in the first DAC cell and on a second voltage difference between the voltage of the first node in the second DAC cell and the voltage of the second node in the second DAC cell.
24. The method of claim 16 , wherein the controlling comprises providing the power supply voltage to a last stage of the switch driver in the at least one of the plurality of DAC cells.
25. The DAC of claim 13 , wherein the power supply voltage is provided to a last stage of the switch driver in the at least one of the plurality of DAC cells.
26. A wireless device comprising the DAC of claim 13 , the wireless device further comprising:
one or more antennas; and
one or more transmit paths coupled between one or more outputs of the DAC and the one or more antennas.