IP Library Granted Patent US 12,165,873
Granted Patent B2
US 12,165,873 · App. 17/739,965 · Granted Dec 10, 2024

Method of manufacturing a semiconductor device

Inventors: En-Ping Lin (Taoyuan, TW); Yu-Ling Ko (Hsinchu, TW); I-Chung Wang (Hsinchu, TW); Yi-Jen Chen (Hsinchu, TW); Sheng-Kai Jou (Taipei, TW); Chih-Teng Liao (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/3065H01L21/308H01L21/823821
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Quick Facts
Patent No.
US 12,165,873
App. No.
17/739,965
Granted
Dec 10, 2024
Kind
B2
Abstract

In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.

Claims (47)

1. A method of manufacturing a semiconductor device, the method comprising:

preparing a p-type region and an n-type region over a substrate, the p-type region including a SiGe layer and the n-type region including a Si layer;

forming a hard mask layer over the SiGe layer and the Si layer;

patterning the hard mask layer to form a hard mask pattern;

patterning the SiGe layer and the Si layer to form fin structures by using an electron cyclotron resonance (ECR) plasma etching apparatus using the hard mask pattern as an etching mask, wherein:

the ECR plasma etching apparatus generates an ECR zone, and

the ECR zone is moved during the patterning the SiGe layer and the Si layer.

2. The method of claim 1 , wherein the patterning the SiGe layer and the Si layer comprises:

patterning the Si layer while covering the p-type region; and

patterning the SiGe layer while covering the n-type region.

3. The method of claim 1 , wherein a pattern pitch in the p-type region is greater than a pattern pitch in the n-type region.

4. The method of claim 1 , wherein the hard mask layer includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

5. The method of claim 1 , wherein the ECR zone is move upwardly at least once and downwardly at least once.

6. The method of claim 1 , wherein the ECR zone is moved in a step-wise manner.

7. The method of claim 1 , wherein the ECR zone is moved twice or more.

8. A method of manufacturing a semiconductor device, comprising:

etching a first region of a substrate to form a recess in the substrate;

forming an epitaxial layer in the recess;

forming a hard mask layer over the first region and a second region of the substrate;

patterning the hard mask layer to form a hard mask pattern;

patterning the first region of the substrate and the second region of the substrate to form one or more fin structures in each region by using an electron cyclotron resonance (ECR) plasma etching apparatus using the hard mask pattern as an etching mask, wherein:

the ECR plasma etching apparatus generates an ECR zone, and

the ECR zone is moved during the patterning the first and second regions of the substrate.

9. The method of claim 8 , wherein the patterning the first region comprises patterning the first region while covering the second region.

10. The method of claim 8 , wherein the patterning the second region comprises patterning the second region while covering the first region.

11. The method of claim 8 , wherein a pattern pitch in the first region is greater than a pattern pitch in the second region.

12. The method of claim 8 , wherein forming the hard mask layer includes:

forming a silicon oxide layer over the substrate; and

forming a silicon nitride layer formed over the silicon oxide layer.

13. The method of claim 8 , wherein the ECR zone is move upwardly at least once and downwardly at least once.

14. The method of claim 8 , wherein the ECR zone is moved in a step-wise manner.

15. The method of claim 8 , wherein the ECR zone is moved twice or more.

16. A method of manufacturing a semiconductor device, comprising:

forming a recess in a first region of a substrate;

forming an epitaxial layer in the recess;

forming a first hard mask layer over the first region and a second region of the substrate;

patterning the hard mask layer to form a hard mask pattern;

etching the first region of the substrate and the second region of the substrate to form one or more fin structures in each region by using an electron cyclotron resonance (ECR) plasma etching apparatus using the hard mask pattern as an etching mask, wherein:

the ECR plasma etching apparatus includes a first coil and a second coil,

the second coil is located closer to the substrate than the first coil, and

during the etching, an input current to the second coil is changed two or more times.

17. The method of claim 16 , wherein a pattern pitch in the first region is greater than a pattern pitch in the second region.

18. The method of claim 16 , wherein forming the hard mask layer includes:

forming a silicon oxide layer over the substrate; and

forming a silicon nitride layer formed over the silicon oxide layer.

19. The method of claim 16 , wherein the ECR plasma etching apparatus generates an ECR zone.

20. The method of claim 19 , wherein the ECR zone is move upwardly at least once and downwardly at least once during the etching.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2022
From: LIN, EN-PING; KO, YU-LING; WANG, I-CHUNG; CHEN, YI-JEN; JOU, SHENG-KAI; LIAO, CHIH-TENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059874/0190 →
Continuity (2)
Continuation 17175396 · Feb 12, 2021
Related Publication 20220270886A1 · Aug 25, 2022