Semiconductor device
A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.
1. A semiconductor device comprising:
an active region extending in a first direction on a substrate;
a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode;
source/drain region disposed on the active region on at least one side of the gate structure;
a first contact structure connected to the source/drain region on the at least one side of the gate structure;
a first gate contact structure disposed on the gate electrode and connected to the gate electrode;
a second contact structure disposed on the first contact structure and connected to the first contact structure; and
a second gate contact structure disposed on the first gate contact structure and connected to the first gate contact structure,
wherein at least one of the second contact structure or the second gate contact structure includes an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer, and
wherein an external surface of the metal liner has surface roughness.
2. The semiconductor device of claim 1 , wherein the at least one of the second contact structure or the second gate contact structure further includes a lower metal layer disposed below the upper metal layer, and
wherein the lower metal layer includes tungsten (W).
3. The semiconductor device of claim 2 , wherein the upper metal layer includes at least one of tungsten (W), molybdenum (Mo), or ruthenium (Ru), and
wherein the metal liner includes tungsten (W).
4. The semiconductor device of claim 2 , wherein the lower metal layer includes a single crystalline tungsten layer, and
wherein the metal liner includes a polycrystalline tungsten layer.
5. The semiconductor device of claim 2 , wherein the metal liner is in direct contact with the lower metal layer and the upper metal layer.
6. The semiconductor device of claim 1 , wherein the lower surface of the upper metal layer includes a concave recess region.
7. The semiconductor device of claim 1 , wherein the metal liner has a first thickness in a vertical direction below the upper metal layer and a second thickness in a horizontal direction on a side surface of the upper metal layer, and
wherein the first thickness is greater than the second thickness.
8. The semiconductor device of claim 1 , wherein the first contact structure includes a metal-semiconductor layer disposed in a recess region of the source/drain region and a contact plug on the metal-semiconductor layer, and
wherein the contact plug includes a metal plug layer and a barrier layer covering a lower surface and side surfaces of the metal plug layer.
9. The semiconductor device of claim 8 , wherein the barrier layer includes tungsten (W), and
wherein an external surface of the barrier layer has surface roughness.
10. The semiconductor device of claim 1 , wherein the first gate contact structure includes a gate contact metal layer and a gate contact plug on the gate contact metal layer, and
wherein the gate contact plug includes a gate metal plug layer, and a barrier layer covering a lower surface and side surfaces of the gate metal plug layer.
11. The semiconductor device of claim 10 , wherein the gate metal plug layer and the barrier layer include tungsten (W), and
wherein an external surface of the barrier layer has surface roughness.
12. A semiconductor device comprising:
an active region extending in a first direction on a substrate;
a gate structure intersecting the active region on the substrate and extending in a second direction;
source/drain region disposed on the active region on at least one side of the gate structure;
a first contact structure connected to the source/drain region on the at least one side of the gate structure; and
a second contact structure disposed on the first contact structure and connected to the first contact structure,
wherein the second contact structure includes a first upper metal layer and a first metal liner covering a lower surface and side surfaces of the first upper metal layer,
wherein the lower surface of the first upper metal layer does not have rough surface and has a concave shape or an inverted V shape, and
wherein an external surface of the first metal liner includes a plurality of uneven portions.
13. The semiconductor device of claim 12 , wherein the first upper metal layer includes at least one of tungsten (W), molybdenum (Mo), or ruthenium (Ru).
14. The semiconductor device of claim 12 , wherein the second contact structure further includes a first lower metal layer disposed between the first metal liner and the first contact structure, and
wherein each of the first lower metal layer and the first metal liner includes tungsten (W).
15. The semiconductor device of claim 12 , wherein a first width of an upper portion of the first contact structure is greater than a second width of a lower portion of the second contact structure.
16. The semiconductor device of claim 12 , wherein a concentration of fluorine (F) element included in the first metal liner is smaller than a concentration of fluorine (F) element included in the first upper metal layer.
17. The semiconductor device of claim 12 , wherein
the gate structure includes:
a gate electrode;
a gate dielectric layer disposed between the active region and the gate electrode;
spacer layers disposed on both sides of the gate electrode; and
a gate capping layer covering an upper surface of the gate electrode between the spacer layers, and
the semiconductor device further includes:
a first gate contact structure being in contact with the gate electrode and penetrating through the gate capping layer; and
a second gate contact structure being in contact with the first gate contact structure on the first gate contact structure.
18. The semiconductor device of claim 17 , wherein the second gate contact structure includes a second lower metal layer, a second upper metal layer on the second lower metal layer, and a second metal liner covering a lower surface and side surfaces of the second upper metal layer, and
wherein an external surface of the second metal liner includes a plurality of uneven portions.
19. A semiconductor device comprising:
a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on a substrate;
a first contact structure penetrating the first interlayer insulating layer on the substrate;
a second contact structure penetrating the second interlayer insulating layer and contacting an upper portion of the first contact structure; and
a metal wiring contacting an upper portion of the second contact structure and extending in a first direction,
wherein the first contact structure includes a metal plug layer and a barrier layer covering a lower surface and side surfaces of the metal plug layer,
wherein the second contact structure includes an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer,
wherein the lower surface of the upper metal layer does not have rough surface and has a concave shape or an inverted V shape, and
wherein a side surface of the second interlayer insulating layer in contact with the metal liner has surface roughness.
20. The semiconductor device of claim 19 , wherein the metal liner includes a plurality of uneven portions corresponding to the surface roughness of the second interlayer insulating layer.