Semiconductor device and method for forming the same
A semiconductor device includes a semiconductor substrate, a doped region formed in the semiconductor substrate, a source/drain formed in the doped region, a conductive pad formed on the source/drain, a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the conductive pad, a gate formed on the gate dielectric layer, an insulation layer formed over the gate, the gate dielectric layer, and the conductive pad, and a contact formed in the insulation layer in electric contact with the conductive pad.
1. A semiconductor device, comprising:
a semiconductor substrate;
a doped region formed in the semiconductor substrate;
a first source/drain and a second source/drain formed in the doped region;
a first conductive pad formed on the first source/drain and a second conductive pad formed on the second source/drain;
a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the first conductive pad and the second conductive pad;
a gate formed on the gate dielectric layer;
an insulation layer formed over the gate, the gate dielectric layer, the first conductive pad, and the second conductive pad; and
a first contact formed in the insulation layer in electric contact with the first conductive pad and a second contact formed in the insulation layer in electric contact with the second conductive pad,
wherein a first entire area of the first conductive pad is fully within a second area of the first source/drain, and a third entire area of the second conductive pad is fully within a fourth area of the second source/drain, and
wherein the first conductive pad fully overlaps the first source/drain, and the second conductive pad fully overlaps the second source/drain.
2. The semiconductor device of claim 1 , wherein the first conductive pad comprises a metal silicide layer.
3. The semiconductor device of claim 2 , wherein the metal silicide layer comprises nickel silicide.
4. The semiconductor device of claim 1 , wherein the gate dielectric layer comprises gate oxide layer.
5. The semiconductor device of claim 1 , wherein the gate dielectric layer consecutively extends above the doped region and under the gate.
6. The semiconductor device of claim 1 , wherein the first conductive pad is surrounded by the gate dielectric layer.
7. The semiconductor device of claim 6 , wherein the first conductive pad is in direct contact with the gate dielectric layer.
8. The semiconductor device of claim 1 , wherein the insulation layer is in contact with the gate dielectric layer.
9. A three-dimensional (3D) memory device, comprising:
a peripheral device, comprising a plurality of transistors, each transistor comprising:
a semiconductor substrate;
a doped region formed in the semiconductor substrate;
a first source/drain and a second source/drain formed in the doped region;
a first conductive pad formed on the first source/drain and a second conductive pad formed on the second source/drain;
a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the first conductive pad and the second conductive pad;
a gate formed on the gate dielectric layer;
an insulation layer formed over the gate, the gate dielectric layer, the first conductive pad, and the second conductive pad; and
a first contact formed in the insulation layer in electric contact with the first conductive pad and a second contact formed in the insulation layer in electric contact with the second conductive pad,
wherein a first entire area of the first conductive pad is fully within a second area of the first source/drain, and a third entire area of the second conductive pad is fully within a fourth area of the second source/drain, and
wherein the first conductive pad fully overlaps the first source/drain, and the second conductive pad fully overlaps the second source/drain; and
a memory stack disposed above the peripheral device.
10. The 3D memory device of claim 9 , wherein the first conductive pad comprises nickel silicide.
11. The 3D memory device of claim 9 , wherein the gate dielectric layer comprises a gate oxide layer.
12. The 3D memory device of claim 9 , wherein the gate dielectric layer consecutively extends above the doped region and under the gate.
13. The 3D memory device of claim 9 , wherein the first conductive pad is surrounded by the gate dielectric layer.
14. The 3D memory device of claim 13 , wherein the first conductive pad is in direct contact with the gate dielectric layer.