Multi-layer barrier for CMOS under array type memory device and method of making thereof

1. A method of forming a semiconductor structure, comprising:

forming a doped semiconductor material portion;

forming a metal-semiconductor alloy portion on the doped semiconductor material portion;

forming a first dielectric material layer over the metal-semiconductor alloy portion;

forming a via cavity through the first dielectric material layer, wherein a top surface of the metal-semiconductor alloy portion is physically exposed;

forming a barrier stack in the via cavity, wherein the barrier stack includes at least two metal nitride layers and at least one silicon or boron layer formed between a pair of the at least two metal nitride layers;

depositing a conductive fill material in a remaining volume of the via cavity; and

performing a thermal treatment to induce diffusion of materials in the barrier stack to convert the silicon or boron layer to a silicon-nitrogen or a boron-nitrogen layer.

2. The method of claim 1 , further comprising converting the at least two metal nitride layers to silicon or boron doped metal nitride layers.

3. The method of claim 1 , wherein:

the doped semiconductor material portion is formed by implanting boron into a substrate semiconductor layer;

the barrier stack comprises a region having a greater concentration of boron atoms than any region within the doped semiconductor material portion after the thermal treatment; and

the region having the greater concentration of boron is spaced from an interface between the metal-semiconductor alloy portion and the barrier stack.

4. The method of claim 1 , wherein the silicon or boron layer is a silicon layer.

5. The method of claim 1 , wherein the silicon or boron layer is a boron layer.

6. The method of claim 1 , wherein:

the silicon or boron layer has a thickness in a range from 0.1 nm to 2.0 nm; and

the barrier stack has a total thickness in a range from 3.0 nm to 25 nm.

7. The method of claim 1 , further comprising:

forming a device contact via structure by removing portions of the conductive fill material and the barrier stack from above a horizontal plane including a top surface of the first dielectric material layer;

forming a second dielectric material layer over the first dielectric material layer;

forming a lower level metal interconnect structure embedded within the second dielectric material layer, wherein the lower level metal interconnect structure is connected to the device contact via structure;

wherein the device contact via structure comprises a source or drain electrode of a peripheral transistor located below a three-dimensional memory array, and the doped semiconductor material portion comprises a source or drain region of the peripheral transistor.