IP Library Granted Patent US 12,176,406
Granted Patent B2
US 12,176,406 · App. 17/113,305 · Granted Dec 24, 2024

Trench MOSFET and method for manufacturing the same

Inventor: Jiakun Wang (Hangzhou, CN)
Assignee: Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd
H01L29/4236H01L29/401H01L29/41775H01L29/66477H01L29/7841
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Quick Facts
Patent No.
US 12,176,406
App. No.
17/113,305
Granted
Dec 24, 2024
Kind
B2
Abstract

A trench MOSFET can include: a semiconductor layer having a first doping type; a trench extending from an upper surface of the semiconductor layer to internal portion of the semiconductor layer; insulating layers and electrode conductors located in the trench; a body region having a second doping type in an upper region of the semiconductor layer adjacent to the trench; and a floating region having the first doping type located in a predetermined position of the semiconductor layer adjacent to both sides of the trench, where the floating region is located below the body region and is separated from the body region.

Claims (26)

1. A trench MOSFET, comprising:

a) a semiconductor layer having a first doping type;

b) a trench extending from an upper surface of the semiconductor layer to internal portion of the semiconductor layer;

c) insulating layers and electrode conductors located in the trench;

d) a body region having a second doping type located in an upper region of the semiconductor layer adjacent to the trench; and

e) a floating region located below the body region and having the first doping type, wherein

when the trench is a vertical trench, a greater doping concentration of the floating region provides a greater distance between an upper surface of the floating region and a bottom surface of the body region and a greater distance between a bottom surface of the floating region and a bottom surface of the trench, and

when the trench is an oblique-angle trench, the distance between the upper surface of the floating region and the bottom surface of the body region is less than the distance between the bottom surface of the floating region and the bottom surface of the trench.

2. The trench MOSFET of claim 1 , wherein the insulating layers in the trench comprise:

a) a first insulating layer covering a lower sidewall surface and a bottom surface of the trench;

b) a second insulating layer covering an upper sidewall surface of the trench;

c) a third insulating layer located between the first insulating layer and the second insulating layer; and

d) wherein the electrode conductors in the trench comprise a first conductor located in a lower part of the trench and a second conductor located in the upper part of the trench, the first insulating layer separates the first conductor from the semiconductor layer, the second insulating layer separates the second conductor from the semiconductor layer, a thickness of the first insulating layer is greater than a thickness of the second insulating layer, and the third insulating layer separates the first conductor from the second conductor.

3. The trench MOSFET of claim 1 , wherein the floating region comprises at least two sub-floating regions, and the sub-floating regions are sequentially arranged along a longitudinal direction of the trench MOSFET.

4. The trench MOSFET of claim 3 , wherein a deeper depth of the trench provides a greater amount of the sub-floating regions.

5. The trench MOSFET of claim 3 , wherein doping concentrations of the sub-floating regions are consistent.

6. The trench MOSFET of claim 3 , wherein:

a) a smaller distance between one of the two sub-floating regions and a bottom surface of the body region provides a lower doping concentration of the sub-floating region; and

b) a smaller distance between one of the two sub-floating regions and a bottom surface of the trench provides a lower doping concentration of the sub-floating region.

7. The trench MOSFET of claim 1 , further comprising:

a) a source region having the first doping type and located in the body region;

b) an interlayer dielectric layer located on the source region, and at least fully covering the trench;

c) a source electrode located on the interlayer dielectric layer, and fully covering the interlayer dielectric layer;

d) a body contact region having the second doping type and located in the body region;

e) a conductive channel penetrating the interlayer dielectric layer and the source region to reach the body contact region; and

f) a drain electrode located under a lower surface of the semiconductor layer, wherein the source electrode is connected to the body contact region through the conductive channel.

Assignments (4)
CHANGE OF NAME Recorded Aug 5, 2025
From: HANGZHOU SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY CO., LTD.
To: SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY (HANGZHOU) CO., LTD.
Reel/Frame 072337/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2021
From: HANGZHOU CHUANGQIN SENSOR TECHNOLOGY CO., LTD.
To: HANGZHOU SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY CO., LTD.
Reel/Frame 058456/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2021
From: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
To: HANGZHOU CHUANGQIN SENSOR TECHNOLOGY CO., LTD.
Reel/Frame 056646/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2020
From: WANG, JIAKUN
To: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
Reel/Frame 054562/0628 →
Continuity (1)
Related Publication 20210184009A1 · Jun 17, 2021