3D semiconductor device and structure with logic circuits and memory cells
A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.
1. A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds; and
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.
2. The 3D device according to claim 1 ,
wherein said single crystal silicon comprises channels adapted for fluid cooling.
3. The 3D device according to claim 1 , further comprising:
a third level,
wherein said third level comprises a plurality of RF circuits.
4. The 3D device according to claim 1 ,
wherein said single crystal silicon comprises an area, and
wherein said area is greater than 1,000 mm 2 .
5. The 3D device according to claim 1 ,
wherein said device comprises a plurality of transmission lines.
6. The 3D device according to claim 1 ,
wherein said memory cells comprise Dynamic Random Access Memory (“DRAM”) cells.
7. The 3D device according to claim 1 ,
wherein said memory cells comprise non-volatile memory cells.
8. A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds,
wherein said single crystal silicon comprises an area, and
wherein said area is greater than 1,000 mm 2 ; and
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.
9. A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds,
wherein said single crystal silicon comprises an area, and
wherein said memory cells comprise Dynamic Random Access Memory (“DRAM”) cells;
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.