Command-differentiated storage of internally and externally sourced data
A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.
1. A memory control component to control a memory integrated-circuit (IC) having a programmable register and a memory core, the memory control component comprising:
a command/address interface; and
control circuitry to output to the memory IC via the command/address interface:
a register-write instruction and corresponding data values, the register-write instruction instructing the memory IC to store the data values within the programmable register; and
a memory access command and an address value, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value.
2. The memory control component of claim 1 further comprising a data interface to output write data to the memory IC, and wherein the control circuitry is further to output, to the memory IC via the command/address interface, a data write command instructing the memory IC to write the write data to the memory core.
3. The memory control component of claim 1 wherein the control circuitry to output the register-write instruction and corresponding data values and to output the memory access command and the address value comprises circuitry to output the register-write instruction and corresponding data values over a first time interval and to output the memory access command and the address value over a second time interval that either commences after the first time interval has transpired or transpires before the first time interval commences.
4. The memory control component of claim 1 wherein the data values and the register-write instruction collectively constitute a register-write command.
5. The memory control component of claim 1 wherein the control circuitry to output the register-write instruction and corresponding data values to the memory IC comprises circuitry to instruct the memory IC to store N data bits within the programmable register, where N is an integer greater than one and each of the N data bits constitutes a respective one of the data values.
6. The memory control component of claim 5 wherein the memory IC comprises an N-bit wide data interface and a command/address interface, and wherein the control circuitry to output the data values and the register-write instruction to the memory IC comprises circuitry to output the data values and the register-write instruction to the command/address interface of the memory IC.
7. The memory control component of claim 1 wherein the memory core of the memory IC comprises a memory cell array and a sense amplifier bank and wherein the control circuitry to output the memory access command to the memory IC via the command/address interface comprises circuitry to instruct the memory IC to store the data values at locations within the sense amplifier bank indicated by the address value.
8. The memory control component of claim 7 wherein the control circuitry to output the memory access command to the memory IC further comprises circuitry to instruct the memory IC to transfer the data values from the locations within the sense amplifier bank to corresponding locations in a row of memory cells within the memory core.
9. The memory control component of claim 7 wherein the control circuitry further comprises circuitry to output a precharge command to the memory IC after outputting the memory access command and the address value, the precharge command instructing the memory IC to transfer the data values from the locations within the sense amplifier bank to corresponding locations in a row of dynamic random access memory cells within the memory core.
10. The memory control component of claim 1 wherein the programmable register of the memory IC comprises two or more component registers, and wherein the register-write instruction instructs the memory IC to store respective subsets of the data values within the two or more component registers.
11. A method of operation within a memory control component for controlling a memory integrated-circuit (IC) having a programmable register and a memory core, the method comprising:
outputting a register-write instruction and corresponding data values to the memory IC via a command/address interface of the memory control component, the register-write instruction instructing the memory IC to store the data values within the programmable register; and
outputting a memory access command and an address value to the memory IC via the command/address interface, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value.
12. The method of claim 11 further comprising outputting a data-write command to the memory IC via the command/address interface of the memory control component, and outputting write data to the memory IC via a data interface of the memory control component, the data-write command instructing the memory IC to write the write data to the memory core.
13. The method of claim 12 wherein outputting the data-write command to the memory IC comprises outputting the data-write command over a time interval that either commences after the register-write instruction has been output to the memory IC or transpires before the first the register-write instruction is output to the memory IC.
14. The method of claim 11 wherein the register-write instruction and corresponding data values collectively constitute a register-write command.
15. The method of claim 11 wherein outputting the register-write instruction and corresponding data values to the memory IC comprises instructing the memory IC to store N data bits within the programmable register, where N is an integer greater than one and each of the N data bits constitutes a respective one of the data values.
16. The method of claim 15 wherein the memory IC comprises an N-bit wide data interface and a command/address interface, and wherein outputting the register-write instruction and corresponding data values to the memory IC comprises outputting the register-write instruction and corresponding data values to the command/address interface of the memory IC.
17. The method of claim 11 wherein the memory core of the memory IC comprises an array of dynamic random access memory (DRAM) cells and wherein outputting the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value comprises instructing the memory IC to write the data values to the array of DRAM cells at locations indicated by the address value.
18. The method of claim 11 wherein the memory core comprises a memory cell array and a sense amplifier bank and wherein outputting the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value comprises instructing the memory IC to (i) store the data values at locations within the sense amplifier bank indicated by the address value, and then (ii) transfer the data values from the locations within the sense amplifier bank to corresponding locations in a row of memory cells within the memory cell array.
19. The method of claim 11 wherein the memory core comprises a memory cell array and a sense amplifier bank and wherein outputting the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value comprises instructing the memory IC to store the data values at locations within the sense amplifier bank indicated by the address value, the method further comprising outputting a precharge command to the memory IC after outputting the memory access command and the address value, the precharge command instructing the memory IC to transfer the data values from the locations within the sense amplifier bank to corresponding locations in a row of dynamic random access memory cells within the memory cell array.
20. A memory control component to control a memory integrated-circuit (IC) having a programmable register and a memory core, the memory control component comprising:
a command/address interface; and
means for outputting to the memory IC via the command/address interface:
a register-write instruction and corresponding data values, the register-write instruction instructing the memory IC to store the data values within the programmable register; and
a memory access command and an address value, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value.