Logic circuits with reduced transistor counts
A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
1. A logic circuit for providing a multibit flip-flop (MBFF) function, the logic circuit comprising:
a first inverter configured to receive a clock signal and generate a corresponding clock_bar signal;
a second inverter configured to receive the clock_bar signal and generate a corresponding clock_bar_bar signal;
a third inverter configured to receive a control signal and generate a corresponding control_bar signal; and
a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each TXFF circuit including:
a NAND circuit configured to receive data signals; and
a 1-bit transmit gate flip-flop (TGFF) circuit configured to:
output signals Q and q; and
receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar signal, the clock_bar_bar signal, the control signal and the control_bar signal; and
a first one of the TXFF circuits in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
2. The logic circuit of claim 1 , wherein:
a total number, N, of the TXFF circuits is N=8 such that the logic circuit provides an 8-bit FF (FF8); and
the logic circuit includes fewer than 264 transistors.
3. The logic circuit of claim 2 , wherein:
the logic circuit includes 248 or fewer transistors.
4. The logic circuit of claim 1 , wherein:
for each TXFF circuit in the series-chain, the TGFF circuit further includes:
a transmission gate;
first to fourth stack-gate-logic (SGL) circuits;
and fourth to sixth inverters; and
for each of the TGFF circuits:
an input of the SGL circuit is configured to receive the control_bar signal;
an output of the first SGL circuit is connected at a first intermediate node to each of an input of the second SGL circuit and an output of the corresponding NAND circuit;
an output of the second SGL circuit is connected at a second intermediate node to each of an output of the third SGL circuit and an input of the fourth inverter;
each of an input of the third SGL circuit and an output of the fourth inverter is connected at a third intermediate node to an input of the transmission gate;
an output of the transmission gate is connected at a fourth intermediate node to each of an output of the fourth SGL circuit and an input of each of the fifth and sixth inverters;
an output of the fifth inverter is connected to a first output node of the TXFF circuit; and
an input of each of the fourth SGL circuit and the sixth inverter are connected to a second output node of the TXFF circuit.
5. The logic circuit of claim 4 , wherein:
each of the first to fourth SGL circuits includes first and second PMOS transistors and first and second NMOS transistors;
the first PMOS transistor is connected between a first reference voltage and the second PMOS transistor;
the second PMOS transistor is connected between the first PMOS transistor and an output node of the SGL circuit;
the first NMOS transistor is connected between the output node of the SGL circuit and the second NMOS transistor; and
the second NMOS transistor is connected between the first NMOS transistor and a second reference voltage.
6. The logic circuit of claim 1 , wherein:
for each TXFF circuit in the series-chain, the TGFF circuit further includes:
a stack-gate-logic (SGL) circuit;
a first sleepy inverter; and
a D flip-flop; and
for each of the TGFF circuits:
an input of the SGL circuit is configured to receive the control_bar signal;
an output of the SGL circuit is connected at a first intermediate node to each of an output of the corresponding NAND circuit and an input of the first sleepy inverter;
an output of the first sleepy inverter is connected at a second intermediate node to an input of the D flip-flop; and
the signals Q and q being on corresponding first and second outputs of the D flip-flop.
7. The logic circuit of claim 6 , wherein:
the first sleepy inverter includes first and second PMOS transistors and first and second NMOS transistors; and
the first PMOS transistor is connected between a first reference voltage and the second PMOS transistor;
the second PMOS transistor is connected between the first PMOS transistor and the second intermediate node;
the first NMOS transistor is connected between the second intermediate node and the second NMOS transistor; and
the second NMOS transistor is connected between the first NMOS transistor and a second reference voltage;
an input of each of the first PMOS transistor and the second NMOS transistor is connected to the first intermediate node;
an input the second PMOS transistor is connected to the clock_bar_bar signal; and
an input of the first NMOS transistor is connected to the clock_bar signal.
8. The logic circuit of claim 6 , wherein:
the D flip-flop includes:
a primary latch;
a transmission gate;
a secondary latch; and
a first non-sleepy inverter;
an input of the primary latch is connected to the second intermediate node;
an output of the primary latch is connected at a third intermediate node to an input of the transmission gate;
an output of the transmission gate is connected at a fourth intermediate node to each of an input of the secondary latch and an input of the first non-sleepy inverter;
the signal Q being an output of the first non-sleepy inverter; and
the signal q being an output of the secondary latch.
9. The logic circuit of claim 8 , wherein:
the primary latch includes:
a second non-sleepy inverter; and
a second sleepy inverter;
each of an input of the second non-sleepy inverter and an output of the second sleepy inverter and is connected to the third intermediate node; and
each of an output of the second non-sleepy inverter and an input of the second sleepy inverter is connected to the fourth intermediate node.
10. The logic circuit of claim 8 , wherein:
the secondary latch includes:
a third non-sleepy inverter; and
a third sleepy inverter;
each of an input of the third non-sleepy inverter and an output of the third sleepy inverter and is connected to the third intermediate node; and
each of an output of the third non-sleepy inverter and an input of the third sleepy inverter is connected to a fifth intermediate node; and
the fifth intermediate node representing the output of the secondary latch.
11. A logic circuit for providing a multibit flip-flop (MBFF) function, the logic circuit comprising:
a first inverter configured to receive a clock signal and generate a corresponding clock_bar signal;
a second inverter configured to receive the clock_bar signal and generate a corresponding clock_bar_bar signal;
a third inverter configured to receive a control signal and generate a corresponding control_bar signal; and
a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each TXFF circuit including:
a NAND circuit configured to receive data signals; and
a 1-bit transmit gate flip-flop (TGFF) circuit configured to:
output signals Q and q; and
receive an output of the NAND circuit, the signal q from from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar signal, the clock_bar_bar signal, the control signal and the control_bar signal;
for each TXFF circuit in the series-chain, the TGFF circuit further including:
a stack-gate-logic (SGL) circuit;
a first sleepy inverter; and
a D flip-flop; and
for each of the TGFF circuits:
an input of the SGL circuit being configured to receive the control_bar signal;
an output of the SGL circuit being connected at a first intermediate node to each of an output of the corresponding NAND circuit and an input of the first sleepy inverter;
an output of the first sleepy inverter being connected at a second intermediate node to an input of the D flip-flop; and
the signals Q and q being on corresponding first and second outputs of the D flip-flop.
12. The logic circuit of claim 11 , wherein:
a first one of the TXFF circuits in the series-chain is configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
13. The logic circuit of claim 11 , wherein:
the first sleepy inverter includes first and second PMOS transistors and first and second NMOS transistors; and
the first PMOS transistor is connected between a first reference voltage and the second PMOS transistor;
the second PMOS transistor is connected between the first PMOS transistor and the second intermediate node;
the first NMOS transistor is connected between the second intermediate node and the second NMOS transistor; and
the second NMOS transistor is connected between the first NMOS transistor and a second reference voltage;
an input of each of the first PMOS transistor and the second NMOS transistor is connected to the first intermediate node;
an input the second PMOS transistor is connected to the clock_bar_bar signal; and
an input of the first NMOS transistor is connected to the clock_bar signal.
14. The logic circuit of claim 11 , wherein:
the D flip-flop includes:
a primary latch;
a transmission gate;
a secondary latch; and
a first non-sleepy inverter;
an input of the primary latch is connected to the second intermediate node;
an output of the primary latch is connected at a third intermediate node to an input of the transmission gate;
an output of the transmission gate is connected at a fourth intermediate node to each of an input of the secondary latch and an input of the first non-sleepy inverter;
the signal Q being an output of the first non-sleepy inverter; and
the signal q being an output of the secondary latch.
15. The logic circuit of claim 14 , wherein:
the primary latch includes:
a second non-sleepy inverter; and
a second sleepy inverter;
each of an input of the second non-sleepy inverter and an output of the second sleepy inverter and is connected to the third intermediate node; and
each of an output of the second non-sleepy inverter and an input of the second sleepy inverter is connected to the fourth intermediate node.
16. The logic circuit of claim 14 , wherein:
the secondary latch includes:
a third non-sleepy inverter; and
a third sleepy inverter;
each of an input of the third non-sleepy inverter and an output of the third sleepy inverter and is connected to the third intermediate node; and
each of an output of the third non-sleepy inverter and an input of the third sleepy inverter is connected to a fifth intermediate node; and
the fifth intermediate node representing the output of the secondary latch.
17. A logic circuit for providing a multibit flip-flop (MBFF) function, the logic circuit comprising:
a first inverter configured to receive a clock signal and generate a corresponding clock_bar signal;
a second inverter configured to receive the clock_bar signal and generate a corresponding clock_bar_bar signal;
a third inverter configured to receive a control signal and generate a corresponding control_bar signal; and
a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each TXFF circuit including:
a NAND circuit configured to receive data signals; and
a 1-bit transmit gate flip-flop (TGFF) circuit configured to:
output signals Q and q; and
receive an output of the NAND circuit, the signal q from from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar signal, the clock_bar_bar signal, the control signal and the control_bar signal; and
a total number, N, of the TXFF circuits is N=8 such that the logic circuit provides an 8-bit FF (FF8); and
the logic circuit includes fewer than 264 transistors.
18. The logic circuit of claim 17 , wherein:
a first one of the TXFF circuits in the series-chain is configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
19. The logic circuit of claim 17 , wherein:
the logic circuit includes 248 or fewer transistors.
20. The logic circuit of claim 17 , wherein:
for each TXFF circuit in the series-chain, the TGFF circuit further includes:
a stack-gate-logic (SGL) circuit;
a first sleepy inverter; and
a D flip-flop; and
for each of the TGFF circuits:
an input of the SGL circuit is configured to receive the control_bar signal;
an output of the SGL circuit is connected at a first intermediate node to each of an output of the corresponding NAND circuit and an input of the first sleepy inverter;
an output of the first sleepy inverter is connected at a second intermediate node to an input of the D flip-flop; and
the signals Q and q being on corresponding first and second outputs of the D flip-flop.