Image sensor having a gate dielectric structure for improved device scaling

1. An image sensor comprising:

a deep trench isolation (DTI) structure disposed in a semiconductor substrate, wherein the DTI structure extends laterally through the semiconductor substrate in a closed loop path, and wherein a pixel region of the semiconductor substrate is disposed within an inner perimeter of the DTI structure;

a photodetector disposed in the pixel region of the semiconductor substrate;

a gate electrode structure partially overlying the pixel region of the semiconductor substrate;

a first gate dielectric structure partially overlying the pixel region of the semiconductor substrate; and

a second gate dielectric structure partially overlying the pixel region of the semiconductor substrate, wherein the gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure, and wherein a thickness of the portion of the second gate dielectric structure is greater than a thickness of the portion of the first gate dielectric structure.

2. The image sensor of claim 1 , further comprising:

a dielectric structure disposed over the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; and

a conductive contact disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact overlies the portion of the second gate dielectric structure.

3. The image sensor of claim 2 , wherein the conductive contact is disposed within the inner perimeter of the DTI structure.

4. The image sensor of claim 2 , wherein the conductive contact at least partially overlies the DTI structure.

5. The image sensor of claim 2 , wherein:

the second gate dielectric structure has a sidewall disposed laterally between a first sidewall of the gate electrode structure and a second sidewall of the gate electrode structure;

the first sidewall of the gate electrode structure is opposite the second sidewall of the gate electrode structure;

the first sidewall of the gate electrode structure faces a sidewall of the DTI structure; and

the conductive contact is disposed laterally between the sidewall of the second gate dielectric structure and the sidewall of the DTI structure.

6. The image sensor of claim 1 , wherein the second gate dielectric structure laterally surrounds the first gate dielectric structure.

7. The image sensor of claim 1 , wherein an outer perimeter of the first gate dielectric structure is disposed within the inner perimeter of the DTI structure.

8. The image sensor of claim 1 , further comprising:

a floating diffusion node disposed in the pixel region of the semiconductor substrate, wherein the floating diffusion node is disposed within an outer perimeter of the first gate dielectric structure.

9. The image sensor of claim 1 , wherein:

the gate electrode structure has a first portion overlying the portion of the first gate dielectric structure;

the gate electrode structure has a second portion overlying the portion of the second gate dielectric structure; and

a height of the first portion of the gate electrode structure is greater than a height of the second portion of the gate electrode structure.

10. The image sensor of claim 1 , further comprising:

a sidewall spacer disposed along sidewalls of the gate electrode structure, wherein a first portion of the sidewall spacer overlies the first gate dielectric structure, wherein a second portion of the sidewall spacer overlies the second gate dielectric structure, and wherein a height of the first portion of the sidewall spacer is greater than a height of the second portion of the sidewall spacer.

11. The image sensor of claim 1 , wherein:

the semiconductor substrate has a first surface and a second surface opposite the first surface;

the first surface of the semiconductor substrate is disposed vertically between the gate electrode structure and the second surface of the semiconductor substrate; and

the first surface of the semiconductor substrate is disposed vertically between a surface of the DTI structure and the second surface of the semiconductor substrate.

12. The image sensor of claim 11 , wherein the DTI structure extends vertically through the semiconductor substrate from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate.

13. An image sensor comprising:

an isolation structure disposed in a semiconductor substrate, wherein the isolation structure extends vertically through the semiconductor substrate from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate;

a floating diffusion node disposed in the semiconductor substrate and on a side of the isolation structure;

a photodetector disposed in the semiconductor substrate and laterally between the floating diffusion node and the isolation structure;

a gate electrode structure disposed over the semiconductor substrate and laterally between the floating diffusion node and the photodetector, wherein the first surface of the semiconductor substrate is disposed vertically between the gate electrode structure and the second surface of the semiconductor substrate;

a first gate dielectric structure disposed over the first surface of the semiconductor substrate; and

a second gate dielectric structure disposed over the first surface of the semiconductor substrate and on a side of the first gate dielectric structure, wherein a thickness of the second gate dielectric structure is greater than a thickness of the first gate dielectric structure, wherein the second gate dielectric structure overlies the isolation structure, and wherein the gate electrode structure partially overlies both the first gate dielectric structure and the second gate dielectric structure.

14. The image sensor of claim 13 , further comprising:

a dielectric structure disposed over the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; and

a conductive contact disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is disposed laterally between a sidewall of the second gate dielectric structure and a sidewall of the isolation structure.

15. The image sensor of claim 14 , wherein a first sidewall of the gate electrode structure is substantially aligned with the sidewall of the isolation structure.

16. The image sensor of claim 15 , wherein:

the first sidewall of the gate electrode structure is opposite a second sidewall of the gate electrode structure;

the first sidewall of the gate electrode structure has a first length; and

the second sidewall of the gate electrode structure has a second length greater than the first length.

17. The image sensor of claim 13 , further comprising:

a dielectric structure disposed over the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; and

a conductive contact disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact partially overlies the isolation structure.

18. The image sensor of claim 17 , wherein:

a sidewall of the second gate dielectric structure is disposed laterally between a first sidewall of the gate electrode structure and a second sidewall of the gate electrode structure;

the first sidewall of the gate electrode structure is opposite the second sidewall of the gate electrode structure; and

the isolation structure is disposed laterally between the sidewall of the second gate dielectric structure and the first sidewall of the gate electrode structure.

19. A method for forming an image sensor, the method comprising:

forming a photodetector in a semiconductor substrate;

forming a first gate dielectric structure over a first side of the semiconductor substrate;

forming a second gate dielectric structure over the first side of the semiconductor substrate, wherein the second gate dielectric structure is formed with a thickness that is greater than a thickness of the first gate dielectric structure;

forming a gate electrode structure partially over the first gate dielectric structure and partially over the second gate dielectric structure;

forming a trench in the semiconductor substrate that exposes a portion of the second gate dielectric structure, wherein the trench is formed from a second side of the semiconductor substrate opposite the first side of the semiconductor substrate; and

forming a back-side deep trench isolation (BDTI) structure in the trench.

20. The method of claim 19 , further comprising:

forming an interlayer dielectric (ILD) structure over the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; and

forming a conductive contact in the ILD structure and electrically coupled to the gate electrode structure, wherein the gate electrode structure has opposite sidewalls, wherein the conductive contact is formed laterally between a first sidewall of the opposite sidewalls of the gate electrode structure and a sidewall of the second gate dielectric structure, and wherein the sidewall of the second gate dielectric structure faces the first gate dielectric structure.