Semiconductor device comprising lightly doped drain (LDD) region between channel and drain region
The purpose of the present invention is to suppress a variation in a threshold voltage (Δ Vth) in a Thin Film Transistor (TFT) using an oxide semiconductor. The present invention takes a structure as follows to attain this purpose. A semiconductor device having TFT using an oxide semiconductor including: a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, in which a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region; a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region; and a thickness of the transition region of the oxide semiconductor is larger than a thickness of the channel region of the oxide semiconductor.
1. A semiconductor device having TFT using an oxide semiconductor comprising:
the oxide semiconductor including a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, wherein
a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region,
a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region,
a thickness of the transition region of the oxide semiconductor is larger than a thickness of the channel region of the oxide semiconductor,
a first gate insulating film covers the oxide semiconductor,
a second gate insulating film covers the first gate insulating film,
a through hole is formed in the second gate insulating film at a place corresponding to the transition region of the oxide semiconductor, and
a gate electrode is formed covering the second gate insulating film and the through hole.
2. The semiconductor device according to claim 1 ,
wherein, in the oxide semiconductor, a thickness of the source region or a thickness of the drain region is larger than a thickness of the transition region.
3. The semiconductor device according to claim 1 ,
wherein, in the oxide semiconductor, a thickness of the channel region is 60 nm or less when measured at a center of the channel region, and a thickness of the transition region measured at a center of the transition region is 85 nm or more.
4. The semiconductor device according to claim 2 ,
wherein, in the oxide semiconductor, a thickness of the channel region is 60 nm or less when measured at a center of the channel region, and a thickness of the transition region measured at a center of the transition region is 85 nm or more.
5. The semiconductor device according to claim 2 ,
wherein a difference in thickness between the source region and the transition region or a difference in thickness between the drain region and the transition region is 10 nm or more.
6. The semiconductor device according to claim 1 ,
wherein a length of the transition region in a direction of a channel length is 2 microns or more.
7. The semiconductor device according to claim 2 ,
wherein a length of the transition region in a direction of channel length is 2 microns or more.
8. The semiconductor device according to claim 3 ,
wherein a length of the transition region in a direction of channel length is 2 microns or more.
9. The semiconductor device according to claim 1 ,
wherein the TFT is a bottom gate type TFT.
10. The semiconductor device according to claim 1 ,
wherein the TFT is a dual gate type TFT which has a bottom gate and a top gate.
11. The semiconductor device according to claim 1 ,
wherein ions are doped in the transition region to raise a conductivity of the oxide semiconductor.
12. A semiconductor device having TFT using an oxide semiconductor comprising:
the oxide semiconductor including a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, wherein
a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region,
a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region,
a first gate insulating film is formed covering the oxide semiconductor,
a second gate insulating film is formed covering the first gate insulating film,
a through hole is formed in the second gate insulating film at a place corresponding the transition region of the oxide semiconductor, and
a gate electrode is formed covering the second insulating film and the through hole.
13. The semiconductor device according to claim 12 ,
wherein a thickness of the transition region is 60 nm or less.
14. The semiconductor device according to claim 12 ,
wherein a length of the transition region in a direction of a channel length is 2 microns or more.
15. The semiconductor device according to claim 12 ,
wherein a third gate insulating film is formed under the oxide semiconductor, and
a second gate electrode is formed under the third gate insulating film.