Oxide thin film transistor, method for manufacturing the same and display device
An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer.
1. An oxide thin film transistor, comprising:
a metal oxide active layer and a source-drain metal layer, which are on a base substrate;
wherein the metal oxide active layer comprises a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; and an electron transfer rate of the first metal oxide layer is greater than an electron transfer rate of the second metal oxide layer;
the first metal oxide layer comprises a primary surface facing toward the base substrate, a primary surface away from the base substrate and a lateral surface coupled to the primary surfaces; and the second metal oxide layer covers at least one of the primary surfaces and the lateral surface of the first metal oxide layer;
a material of the first metal oxide layer comprises a metal oxide in an amorphous state; and
a material of the second metal oxide layer comprises a metal oxide in a crystalline state and has a crystallization peak in a range of 29° to 32° in an X-ray diffraction spectrogram.
2. The oxide thin film transistor according to claim 1 , wherein the source-drain metal layer is at a side of the second metal oxide layer away from the first metal oxide layer; a via hole or a blind hole is defined in the second metal oxide layer; the via hole or the blind hole extends in a direction perpendicular to the base substrate; and the source-drain metal layer is electrically coupled to the first metal oxide layer through the via hole or the blind hole.
3. The oxide thin film transistor according to claim 1 , wherein the first metal oxide layer has a band gap of 2.3 to 2.8 eV; and the second metal oxide layer has a band gap of 2.8 to 3.5 eV.
4. The oxide thin film transistor according to claim 1 , wherein a density of the primary surfaces of the first metal oxide layer is greater than a density of the lateral surface of the first metal oxide layer.
5. A display device, comprising: the oxide thin film transistor according to claim 1 .
6. The oxide thin film transistor according to claim 1 , wherein a total thickness of the first metal oxide layer and the second metal oxide layer is not greater than 100 nanometers; and a thickness of the second metal oxide layer is greater than a thickness of the first metal oxide layer.
7. The oxide thin film transistor according to claim 6 , wherein the source-drain metal layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked on each other.
8. The oxide thin film transistor according to claim 1 , wherein the material of at least one of the first metal oxide layer and the material of the second metal oxide layer comprises indium gallium zinc oxide (IGZO).
9. The oxide thin film transistor according to claim 8 , wherein the active layer further comprises a third metal oxide layer; the third metal oxide layer is at a side of the first metal oxide layer away from the second metal oxide layer; a range of an orthographic projection of the first metal oxide layer onto the third metal oxide layer is less than or equal to a range of the third metal oxide layer; the third metal oxide layer has the same material and degree of crystallization as the second metal oxide layer.
10. The oxide thin film transistor according to claim 8 , wherein the active layer further comprises a fourth metal oxide layer; the fourth metal oxide layer is at a side of the second metal oxide layer away from the first metal oxide layer; and the fourth metal oxide layer covers a lateral surface of the second metal oxide layer in a direction perpendicular to the base substrate;
a material of the fourth metal oxide layer comprises IGZO, a degree of crystallization of the material of the fourth metal oxide layer is greater than a degree of crystallization of the material of the second metal oxide layer; and the fourth metal oxide layer has a band gap of 3.0 to 3.5 eV.
11. The oxide thin film transistor according to claim 10 , wherein an atomic percentage of indium in a metal material of the fourth metal oxide layer is smaller than an atomic percentage of indium in a metal material of the second metal oxide layer.
12. The oxide thin film transistor according to claim 11 , wherein an atomic number ratio of indium, gallium and zinc in the metal material of the fourth metal oxide layer is 2:5-8:5-8.
13. An oxide thin film transistor, comprising:
a metal oxide active layer and a source-drain metal layer, which are on a base substrate;
wherein the metal oxide active layer comprises a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; and an electron transfer rate of the first metal oxide layer is greater than an electron transfer rate of the second metal oxide layer;
a total thickness of the first metal oxide layer and the second metal oxide layer is not greater than 100 nanometers; and a thickness of the second metal oxide layer is greater than a thickness of the first metal oxide layer;
a material of the first metal oxide layer comprises a metal oxide in an amorphous state; and
a material of the second metal oxide layer comprises a metal oxide in a crystalline state and has a crystallization peak in a range of 29° to 32° in an X-ray diffraction spectrogram.
14. The oxide thin film transistor according to claim 13 , wherein the source-drain metal layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked on each other; the third sub-layer is electrically coupled to the first metal oxide layer through the via hole or the blind hole.
15. A display device, comprising: the oxide thin film transistor according to claim 13 .
16. A method of manufacturing an oxide thin film transistor, comprising:
a step of fabricating an active layer; and
a step of fabricating a source-drain metal layer;
wherein the step of fabricating the active layer, comprises:
fabricating a pattern of a first metal oxide layer through a first patterning process with a target mask; and
fabricating a pattern of a second metal oxide layer through a second patterning process with the target mask;
wherein an electron transfer rate of the first metal oxide layer is greater than an electron transfer rate of the second metal oxide layer; a line width of the first patterning process is greater than a line width of the second patterning process; an exposure time of the first patterning process is less than an exposure time of the second patterning process; and a developing time of the first patterning process is less than a developing time of the second patterning process.
17. The method according to claim 16 , wherein fabricating the pattern of the first metal oxide layer through the first patterning process with the target mask, and fabricating the pattern of the second metal oxide layer through the second patterning process with the target mask, comprises:
controlling an etching rate of the first metal oxide layer to be less than an etching rate of the second metal oxide layer.
18. The method according to claim 16 , wherein the line width of the first patterning process is greater than the line width of the second patterning process by 0.1 to 0.5 microns; and/or
the exposure time of the first patterning process is less than the exposure time of the second patterning process by 30 to 200 milliseconds; and/or
the developing time of the first patterning process is less than the developing time of the second patterning process by 1 to 10 seconds.