Granted Patent B2

US 12,197,342 · App. 18/178,568 · Granted Jan 14, 2025

Inventor: Toru Hikichi (Inagi, JP)

Assignee: FUJITSU LIMITED

G06F12/0895G06F12/0833

Abstract

Claims (17)

1. An arithmetic processing device comprising:

an arithmetic circuit that executes an instruction;

a first cache which is coupled to the arithmetic circuit and which has a plurality of first entries each including a first tag region and a first data region that holds cache line data;

a processor which includes a second tag region and controls the first cache based on information held in the second tag region; and

a second cache which is coupled to the first cache via the processor and which includes a plurality of second entries each of which includes a third tag region and a second data region that holds cache line data,

the second tag region includes a first region that holds first information which specifies whether or not the second data region holds cache line data which has the same address as the address of cache line data held in the first data region, and in accordance with the first information held in the second tag region which corresponds to write-back target cache line data, the processor determines whether a write-back location to which the cache line data held in the first cache is to be written back is the second cache or an external memory.

2. The arithmetic processing device according to claim 1 , wherein in a case where cache line data is to be transferred from the second cache to the first cache, the processor sets the first information in association with the cache line data to be transferred to a value which indicates that the second cache is the write-back location, and in a case where cache line data which has the same address as the address of the cache line data held in the first cache is to be written back from the second cache to the external memory, the processor sets the first information which corresponds to the cache line data to be written back to a value which indicates that the external memory is the write-back location.

3. The arithmetic processing device according to claim 2 , wherein in a case where, in searching the second tag region for an access target address, an entry is detected in which a bit value which corresponds to an index address of the third tag region matches the index address and a bit value which corresponds to a tag address of the third tag region does not match the tag address, the processor sets the first information of the detected entry to a value which indicates that the external memory is the write-back location.

4. The arithmetic processing device according to claim 1 , wherein the second tag region includes a second region that holds second information that is set in a case where the cache line data held in the first cache is written back to the external memory and cache line data which has the same address as the address of the cache line data written back remains in the second cache, and in a case where the second information in association with write-back target cache line data held in the second cache is set, the processor keeps the write-back target cache line data from being written back from the second cache to the external memory.

5. The arithmetic processing device according to claim 1 , wherein the arithmetic circuit and the first cache are included in one of a plurality of cache blocks and the processor is disposed between the plurality of cache blocks and the second cache.

6. The arithmetic processing device according to claim 4 , wherein the second tag region includes the first region and a region that holds part of a plurality of types of tag information held in the first tag region.

7. The arithmetic processing device according to claim 1 , wherein the second tag region and the processor are included in the first cache.

8. The arithmetic processing device according to claim 1 , wherein each of the plurality of first entries in the first cache has a plurality of ways, and each of the plurality of second entries in the second cache has a single way.

9. The arithmetic processing device according to claim 1 , comprising a die on which the arithmetic circuit and the first cache which are included in one of a plurality of cache blocks are mounted; and a package in which the die and the second cache are mounted, wherein the processor is coupled to the external memory disposed outside the package.

10. An arithmetic processing device comprising:

controlling, by a processor which includes a second tag region which includes a first region that holds first information which specifies whether or not the second data region holds cache line data which has the same address as the address of cache line data held in the first data region and is included in an arithmetic processing device including an arithmetic circuit that executes an instruction, a first cache which is coupled to the arithmetic circuit and which has a plurality of first entries each including a first tag region and a first data region that holds cache line data, and a second cache which is coupled to the first cache via the processor; and

in accordance with the first information held in the second tag region which corresponds to write-back target cache line data, determining whether a write-back location to which the cache line data held in the first cache is to be written back is the second cache or an external memory.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (21)