Methods and systems for requesting atomic operations in a computing system
Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.
1. A computing system comprising:
a first hardware compute element;
a second hardware compute element; and
a network structure, the computing system being configured to perform operations comprising:
sending, by a first hardware compute element, a first request via a network structure, the first request comprising an atomic opcode indicating an atomic operation to be performed by a second hardware compute element;
providing, by the network structure, an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element;
executing, by the second hardware compute element, the atomic operation;
sending, by the second hardware compute element, confirmation data indicating completion of the atomic operation; and
providing, by the network structure a second bus from the second hardware compute element and the first hardware compute element, the second bus for providing the confirmation data from the second hardware compute element to the first hardware compute element.
2. The computing system of claim 1 , the atomic operation being an atomic store operation and the first request also comprising request data to be stored by the second hardware compute element, the operations further comprising:
providing, by the network structure, a first request data bus from the first hardware compute element for providing the request data to the second hardware compute element; and
the second bus being a write confirmation bus.
3. The computing system of claim 2 , the address bus comprising a first channel for providing the atomic opcode and a second channel for providing address data indicating the second hardware compute element.
4. The computing system of claim 1 , the atomic operation being an atomic load operation, the first request comprising a data identifier describing data to be loaded.
5. The computing system of claim 4 , the second bus being a read data bus and the confirmation data comprising read data indicated by the data identifier.
6. The computing system of claim 4 , the first request further comprising operation data, the atomic opcode describing an operation that is based on the data to be loaded and the operation data.
7. The computing system of claim 6 , the address bus comprising a first channel for providing the atomic opcode, a second channel for providing the data identifier, and a third channel for providing the operation data.
8. The computing system of claim 1 , the first request also comprising:
sending, by the first hardware compute element, the first request to a hardware load balancer element; and
sending a second request, by the hardware load balancer element, to the second hardware compute element, the second request comprising the atomic opcode.
9. The computing system of claim 1 , the address bus being provided between the first hardware compute element and the second hardware compute element.
10. A method of requesting an atomic operation between compute elements of a computing system, the method comprising:
sending, by a first hardware compute element, a first request via a network structure, the first request comprising an atomic opcode indicating an atomic operation to be performed by a second hardware compute element;
providing, by the network structure, an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element;
executing, by the second hardware compute element, the atomic operation;
sending, by the second hardware compute element, confirmation data indicating completion of the atomic operation; and
providing, by the network structure a second bus from the second hardware compute element and the first hardware compute element, the second bus for providing the confirmation data from the second hardware compute element to the first hardware compute element.
11. The method of claim 10 , the atomic operation being an atomic store operation and the first request also comprising request data to be stored by the second hardware compute element, the method further comprising:
providing, by the network structure, a first request data bus from the first hardware compute element for providing the request data to the second hardware compute element; and
the second bus being a write confirmation bus.
12. The method of claim 11 , the address bus comprising a first channel for providing the atomic opcode and a second channel for providing address data indicating the second hardware compute element.
13. The method of claim 10 , the atomic operation being an atomic load operation, the first request comprising a data identifier describing data to be loaded.
14. The method of claim 13 , the second bus being a read data bus and the confirmation data comprising read data indicated by the data identifier.
15. The method of claim 13 , the first request further comprising operation data, the atomic opcode describing an operation that is based on the data to be loaded and the operation data.
16. The method of claim 15 , the address bus comprising a first channel for providing the atomic opcode, a second channel for providing the data identifier, and a third channel for providing the operation data.
17. The method of claim 10 , the first request also comprising:
sending, by the first hardware compute element, the first request to a hardware load balancer element; and
sending a second request, by the hardware load balancer element, to the second hardware compute element, the second request comprising the atomic opcode.
18. The method of claim 10 , the address bus being provided between the first hardware compute element and the second hardware compute element.
19. A non-transitory machine-readable medium comprising instructions thereon, that when executed by a system comprising a first hardware compute element, a second hardware compute element, and a network structure, cause the system to perform operations comprising:
sending, by a first hardware compute element, a first request via a network structure, the first request comprising an atomic opcode indicating an atomic operation to be performed by a second hardware compute element;
providing, by the network structure, an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element;
executing, by the second hardware compute element, the atomic operation;
sending, by the second hardware compute element, confirmation data indicating completion of the atomic operation; and
providing, by the network structure a second bus from the second hardware compute element and the first hardware compute element, the second bus for providing the confirmation data from the second hardware compute element to the first hardware compute element.
20. The medium of claim 19 , the atomic operation being an atomic store operation and the first request also comprising request data to be stored by the second hardware compute element, the operations further comprising:
providing, by the network structure, a first request data bus from the first hardware compute element for providing the request data to the second hardware compute element; and
the second bus being a write confirmation bus.