IP Library › Granted Patent US 12,481,537
Granted Patent B2
US 12,481,537 · App. 17/813,763 · Granted Nov 25, 2025

Methods and systems for communications between hardware components

Inventors: Christopher Baronne (Allen, TX); Michael Keith Dugan (Richardson, TX); Bryan Hornung (Plano, TX)
Assignee: Micron Technology, Inc.
G06F9/505G06F9/4881G06F9/546G06F9/5083G06F15/7821G06F15/7825
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Quick Facts
Patent No.
US 12,481,537
App. No.
17/813,763
Granted
Nov 25, 2025
Kind
B2
Abstract

Various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. The first hardware compute element may send a first request message to a hardware balancer element. The first request message may describe a processing task. The hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. After sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.

Claims (48)

1 . An apparatus comprising:

a first hardware compute element, the first hardware compute element being programmed to perform operations comprising sending a first request message to a hardware balancer element, the first request message describing a processing task; and

the hardware balancer element being programmed to perform operations comprising:

sending a second request message towards a second hardware compute element for executing the processing task, the second request message also describing the processing task;

sending, to the first hardware compute element, a first reply message, the first reply message being in reply to the first request message;

after sending the first reply message, receiving a first completion request message, the first completion request message indicating that the processing task is assigned; and

sending, to the first hardware compute element, a second completion request message, the second completion request message indicating that the processing task is assigned.

2 . The apparatus of claim 1 , the operations further comprising selecting the second hardware compute element by the hardware balancer element.

3 . The apparatus of claim 2 , wherein sending the second request message towards the second hardware compute element comprises directing the second request message to the second hardware compute element.

4 . The apparatus of claim 1 , wherein sending the second request message towards the second hardware compute element comprises sending the second request message to a second hardware balancer element, and wherein the first completion request message is received from the second hardware compute element.

5 . The apparatus of claim 4 , the operations further comprising sending, by the hardware balancer element, a first completion reply message to the second hardware balancer element.

6 . The apparatus of claim 4 , wherein the sending of the first request message is via a first network structure, the operations further comprising:

sending, by the second hardware balancer element and to the second hardware compute element, a third request message describing the processing task, the third request message being sent via a second network structure different than the first network structure; and

sending, by the second hardware compute element and to the second hardware balancer element, a second reply message in reply to the third request message, the second reply message indicating that the processing task is assigned.

7 . The apparatus of claim 6 , the operations further comprising:

responsive to the sending of the third request message, storing, by the second network structure, state data describing the third request message; and

responsive to the sending of the first reply message, clearing the state data describing the third request message.

8 . The apparatus of claim 4 , the operations further comprising selecting the second hardware compute element by the second hardware balancer element.

9 . The apparatus of claim 1 , wherein the sending of the first request message is via a first network structure, the operations further comprising:

responsive to the sending of the first request message, storing, by the first network structure, state data describing the first request message; and

responsive to the sending of the first reply message, clearing the state data describing the first request message by the first network structure.

10 . A method, comprising:

sending, by a first hardware compute element, a first request message to a hardware balancer element, the first request message describing a processing task;

sending, by the hardware balancer element, a second request message towards a second hardware compute element for executing the processing task, the second request message also describing the processing task;

sending, by the hardware balancer element and to the first hardware compute element, a first reply message, the first reply message being in reply to the first request message;

after sending the first reply message, receiving, by the hardware balancer element, a first completion request message, the first completion request message indicating that the processing task is assigned; and

sending, by the hardware balancer element and to the first hardware compute element, a second completion request message, the second completion request message indicating that the processing task is assigned.

11 . The method of claim 10 , the method further comprising selecting the second hardware compute element by the hardware balancer element.

12 . The method of claim 11 , wherein sending the second request message towards the second hardware compute element comprises directing the second request message to the second hardware compute element.

13 . The method of claim 10 , wherein sending the second request message towards the second hardware compute element comprises sending the second request message to a second hardware balancer element, and wherein the first completion request message is received from the second hardware compute element.

14 . The method of claim 13 , further comprising sending, by the hardware balancer element, a first completion reply message to the second hardware balancer element.

15 . The method of claim 13 , wherein the sending of the first request message is via a first network structure, the method further comprising:

sending, by the second hardware balancer element and to the second hardware compute element, a third request message describing the processing task, the third request message being sent via a second network structure different than the first network structure; and

sending, by the second hardware compute element and to the second hardware balancer element, a second reply message in reply to the third request message, the second reply message indicating that the processing task is assigned.

16 . The method of claim 15 , further comprising:

responsive to the sending of the third request message, storing, by the second network structure, state data describing the third request message; and

responsive to the sending of the first reply message, clearing the state data describing the third request message.

17 . The method of claim 13 , further comprising selecting the second hardware compute element by the second hardware balancer element.

18 . The method of claim 10 , wherein the sending of the first request message is via a first network structure, the method further comprising:

responsive to the sending of the first request message, storing, by the first network structure, state data describing the first request message; and

responsive to the sending of the first reply message, clearing the state data describing the first request message by the first network structure.

19 . At least one non-transitory computer readable medium comprising instructions thereon that, when executed by at least one hardware component, cause the at least one hardware component to perform operations comprising:

sending, by a first hardware compute element, a first request message to a hardware balancer element, the first request message describing a processing task;

sending, by the hardware balancer element, a second request message towards a second hardware compute element for executing the processing task, the second request message also describing the processing task;

sending, by the hardware balancer element and to the first hardware compute element, a first reply message, the first reply message being in reply to the first request message;

after sending the first reply message, receiving, by the hardware balancer element, a first completion request message, the first completion request message indicating that the processing task is assigned; and

sending, by the hardware balancer element and to the first hardware compute element, a second completion request message, the second completion request message indicating that the processing task is assigned.

20 . The medium of claim 19 , the operations further comprising selecting the second hardware compute element by the hardware balancer element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2022
From: BARONNE, CHRISTOPHER; DUGAN, MICHAEL KEITH; HORNUNG, BRYAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 062040/0001 →
Continuity (1)
Related Publication 20240028390A1 · Jan 25, 2024
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