Semiconductor package comprising first molding layer and second molding layer with different thermal expansion coefficients
A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.
1. A semiconductor package comprising:
an upper structure comprising a semiconductor chip and a first molding layer for molding the semiconductor chip;
a lower structure provided on the upper structure, the lower structure comprising a conductive post and a second molding layer for molding the conductive post; and
a redistribution structure provided between the upper structure and the lower structure, the redistribution structure comprising a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post,
wherein a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer;
wherein the first molding member and the second molding member are spaced apart from each other in a vertical direction with the redistribution structure interposed therebetween; and
wherein the thermal expansion coefficient of the first molding member overlapping the semiconductor chip in a horizontal direction is smaller than the thermal expansion coefficient of the second molding member not overlapping the semiconductor chip in the horizontal direction.
2. The semiconductor package of claim 1 , wherein
the redistribution structure comprises an insulating pattern covering the wiring pattern, and
the conductive post comprises a first portion surrounded by the insulating pattern and a second portion surrounded by the second molding layer.
3. The semiconductor package of claim 2 , wherein a width of the first portion of the conductive post is less than a width of the second portion of the conductive post.
4. The semiconductor package of claim 2 , wherein a thickness of the first portion is smaller than a thickness of the second portion.
5. The semiconductor package of claim 2 , wherein a thickness of the second molding layer is greater than a thickness of the insulating pattern.
6. The semiconductor package of claim 1 , further comprising an external connection terminal directly connected to one end of the conductive post.
7. The semiconductor package of claim 1 , wherein the lower structure further comprises a lower insulating layer provided on the second molding layer and comprises an opening for exposing the conductive post.
8. The semiconductor package of claim 1 , further comprising a lower redistribution structure provided on the lower structure, the lower redistribution structure comprising a lower wiring pattern electrically connected to the conductive post and a lower insulating pattern covering the lower wiring pattern.
9. The semiconductor package of claim 1 , wherein the upper structure further comprises a heat dissipation plate provided on the semiconductor chip.
10. The semiconductor package of claim 1 , wherein the second molding layer comprises a plurality of sub-molding layers that are sequentially stacked on the redistribution structure, and the plurality of sub-molding layers have thermal expansion coefficients that are different from each other.
11. The semiconductor package of claim 10 , wherein:
the plurality of sub-molding layers includes a first sub-molding layer and a second sub- molding layer; and
a thermal expansion coefficient of the first sub-molding layer is between the thermal expansion coefficient of the first molding layer and a thermal expansion coefficient of the second sub-molding layer.
12. The semiconductor package of claim 1 , wherein:
the semiconductor package is disposed on a circuit board; and
the thermal expansion coefficient of the second molding layer is between the thermal expansion coefficient of the first molding layer and a thermal expansion coefficient of the circuit board.
13. A semiconductor module comprising:
a circuit board; and
a semiconductor package disposed on the circuit board,
wherein the semiconductor package comprises:
a semiconductor chip;
a first molding layer surrounding the semiconductor chip and having a first thermal expansion coefficient;
a redistribution structure including a wiring pattern electrically connected to the semiconductor chip;
a second molding layer provided between the first molding layer and the circuit board in a vertical direction and having a second thermal expansion coefficient between a thermal expansion coefficient of the circuit board and the first thermal expansion coefficient;
a conductive post passing through the second molding layer and electrically connected to the wiring pattern; and
an external connection terminal configured to electrically connect the conductive post and a substrate pad of the circuit board;
wherein the first molding member and the second molding member are spaced apart from each other in the vertical direction with the redistribution structure interposed therebetween; and
wherein the thermal expansion coefficient of the first molding member overlapping the semiconductor chip in a horizontal direction is smaller than the thermal expansion coefficient of the second molding member not overlapping the semiconductor chip in the horizontal direction.