Shallow trench isolation processing with local oxidation of silicon
A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.
1. An electronic device, comprising:
a semiconductor surface layer extending in a plane of orthogonal first and second directions;
a first isolation structure having a dielectric material in a trench of the semiconductor surface layer, the dielectric material having a first side, a second side, and an indent, the first side on a surface of the trench, the first side spaced apart from the second side along a third direction, the third direction orthogonal to the first and second directions, the indent extending into the first side along the third direction, the indent filled with a semiconductor material of the semiconductor surface layer, and an end of the indent spaced apart from the second side along the third direction by a gap distance, the gap distance being 20 nm or more, and the gap distance less than a first thickness of the dielectric material along the third direction;
a second isolation structure spaced apart from the first isolation structure, the second isolation structure having a thermally grown dielectric material including the semiconductor material, wherein the thermally grown dielectric material has a second thickness along the third direction that is less than the first thickness; and
a passive circuit component having a doped polysilicon structure on the second side of the dielectric material.
2. The electronic device of claim 1 , wherein the gap distance is 50 nm or more.
3. The electronic device of claim 2 , wherein the dielectric material has a thickness along the third direction of 350 nm or more.
4. The electronic device of claim 1 , wherein the second thickness of the second isolation structure is greater than the gap distance.
5. The electronic device of claim 1 , wherein the passive circuit component is a resistor.
6. The electronic device of claim 1 , wherein the passive circuit component is a capacitor, and the doped polysilicon structure is a first capacitor plate of the capacitor.
7. The electronic device of claim 1 , wherein the dielectric material has a thickness along the third direction of 350 nm or more.
8. The electronic device of claim 5 , wherein the resistor includes a first contact proximate a first end of the doped polysilicon structure and a second contact proximate a second end of the doped polysilicon structure.
9. The electronic device of claim 6 , wherein the capacitor includes a second capacitor plate that is spaced apart from the first capacitor plate along the third direction, the second capacitor plate includes conductive metal.
10. The electronic device of claim 1 , wherein the second isolation structure is formed after the first isolation structure.
11. A semiconductor device, comprising:
a semiconductor layer;
a first isolation structure in a trench of the semiconductor layer, the first isolation structure including a dielectric material with a first side on a surface of the trench, a second side opposite the first side, and an indent extending into the first side, wherein:
the indent includes a material of the semiconductor layer; and
an end of the indent is spaced apart from the second side by a distance less than a first thickness of the dielectric material; and
a second isolation structure spaced apart from the first isolation structure, the second isolation structure including a thermally grown dielectric material having the material of the semiconductor layer and having a second thickness less than the first thickness.
12. The semiconductor device of claim 11 , wherein the distance is 20 nm or more.
13. The semiconductor device of claim 11 , wherein the first thickness is 350 nm or more.
14. The semiconductor device of claim 11 , wherein the second thickness is greater than the distance.
15. The semiconductor device of claim 11 , wherein the second isolation structure is formed after the first isolation structure.
16. The semiconductor device of claim 11 , further comprising:
a passive component including a polysilicon structure on the second side of the dielectric material.
17. The semiconductor device of claim 16 , wherein the passive component is a resistor.
18. The semiconductor device of claim 17 , wherein the resistor includes a first contact near a first end of the polysilicon structure and a second contact near a second end of the polysilicon structure.
19. The semiconductor device of claim 16 , wherein the passive component is a capacitor, and the polysilicon structure is a first plate of the capacitor.
20. The semiconductor device of claim 19 , further comprising:
a second plate of the capacitor spaced apart from the first plate, wherein:
the second plate has conductive metal; and
a footprint of the second plate at least partially overlaps the first plate.
21. The semiconductor device of claim 11 , further comprising:
a field effect transistor spaced apart from the first isolation structure, the field effect transistor including a polysilicon gate.
22. The semiconductor device of claim 21 , further comprising:
a passive component including a polysilicon structure on the second side of the dielectric material, wherein the polysilicon structure is concurrently formed with the polysilicon gate.