Physical downlink control channel candidate resource mapping and transmission for multi-TRP operation
A base station maps physical downlink control channel (PDCCH) candidates and PDCCH transmissions for multi-transmission reception point (TRP) operation. The base station determines that a control resource set (CORESET) is to be shared by at least a first TRP and a second TRP corresponding to a cell of a network, performs resource element group (REG) bundle to virtual REG bundle mapping on a per TRP basis, wherein multiple REG bundles are indexed on the per TRP basis, performs virtual REG bundle interleaving across the first TRP and the second TRP, performs control channel element (CCE) to interleaved REG bundle mapping and transmits downlink control information (DCI) using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping.
1. A processor configured to perform operations comprising:
determining that a control resource set (CORESET) is to be shared by at least a first transmission reception point (TRP) and a second TRP corresponding to a cell of a network;
performing resource element group (REG) bundle to virtual REG bundle mapping on a per TRP basis, wherein multiple REG bundles are indexed on the per TRP basis;
performing virtual REG bundle interleaving across the first TRP and the second TRP by
determining a number of columns for a matrix based on, at least, a number of REG in the CORESET;
determining a number of rows for the matrix based on, at least, a number of TRPs sharing the CORESET;
inputting a first virtual REG bundle sequence into the matrix, and
generating a second virtual REG bundle sequence based on, at least, the matrix;
performing control channel element (CCE) to interleaved REG bundle mapping; and
transmitting downlink control information (DCI) using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping.
2. The processor of claim 1 , wherein the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle and TRP.
3. The processor of claim 1 , wherein the operations further:
determining whether an even CCE index or an odd CCE index is to be utilized;
when the even CCE index is to be utilized, the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the first TRP; and
when the odd CCE index is to be utilized, the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the second TRP.
4. The processor of claim 1 , wherein the operations further comprise:
shifting REG bundles in different TRPs when constructing a CCE based on a shifting parameter.
5. The processor of claim 4 , wherein the shifting parameter is a function of a TRP index.
6. The processor of claim 4 , wherein the shifting parameter is configured by higher layer signaling.
7. The processor of claim 4 , wherein the shifting parameter is configured on a per CORESET basis.
8. A processor configured to perform operations comprising:
monitoring a physical downlink control channel (PDCCH) for downlink control information (DCI) transmitted by a cell of a network;
wherein monitoring the PDCCH includes identifying a set of PDCCH candidates that is based on a control channel element (CCE) bundle,
wherein the PDCCH includes the CCE bundle within a control resource set (CORESET) and the CCE bundle corresponds to a single transmission reception point (TRP),
wherein the CCE bundle is based on, at least, the single TRP and an aggregation level;
receiving the DCI carried by the PDCCH from the cell of the network; and
performing an operation in response to the DCI.
9. The processor of claim 8 , wherein the CCE bundle is indexed is based on, at least, a TRP index and frequency.
10. The processor of claim 8 , wherein the PDCCH includes the CCE bundle across CCEs of multiple transmission reception points (TRPS).
11. The processor of claim 10 , wherein the CCE bundle includes multiple CCE pairs, wherein each CCE pair includes a first CCE for a first TRP and a second CCE for a second TRP.
12. The processor of claim 10 , wherein the CCE bundle is indexed in increasing order of frequency.
13. The processor of claim 8 , wherein the PDCCH includes a first control resource set (CORESET) corresponding to a first transmission reception point (TRP) and a second CORESET that is shared by the first TRP and a second TRP.
14. A cell, comprising:
a communication interface configured to communicate with a user equipment (UE); and
a processor communicatively coupled to the communication interface and configured to perform operations comprising:
determining that a control resource set (CORESET) is to be shared by at least a first transmission reception point (TRP) and a second TRP of the cell;
performing resource element group (REG) bundle to virtual REG bundle mapping on a per TRP basis, wherein multiple REG bundles are indexed on the per TRP basis;
performing virtual REG bundle interleaving across the first TRP and the second TRP by
determining a number of columns for a matrix based on, at least, a number of REG in the CORESET;
determining a number of rows for the matrix based on, at least, a number of TRPs sharing the CORESET;
inputting a first virtual REG bundle sequence into the matrix, and
generating a second virtual REG bundle sequence based on, at least, the matrix;
performing control channel element (CCE) to interleaved REG bundle mapping; and
transmitting downlink control information (DCI) using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping.
15. The cell of claim 14 , further comprising:
shifting REG bundles in different TRPs when constructing a CCE based on a shifting parameter.