IP Library › Granted Patent US 12,200,937
Granted Patent B2
US 12,200,937 · App. 18/503,809 · Granted Jan 14, 2025

Semiconductor device and method of manufacturing semiconductor device

Inventors: Moon Sik Seo (Icheon-si, KR); Dae Hwan Yun (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B43/27H01L21/0214H01L21/02164H01L21/0223H01L29/40114H01L29/40117H10B41/27H10B63/34H10B63/845H10N70/041H10N70/066
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Quick Facts
Patent No.
US 12,200,937
App. No.
18/503,809
Granted
Jan 14, 2025
Kind
B2
Abstract

A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

Claims (18)

1. A semiconductor device comprising:

a gate structure with alternately stacked conductive layers and insulating layers;

a channel layer passing through the gate structure;

a memory layer positioned between the channel layer and the conductive layers; and

barrier patterns positioned between the channel layer and the insulating layers and separated from each other by the memory layer,

wherein each of the barrier patterns includes a sidewall facing the memory layer, and the sidewall includes a curved surface.

2. The semiconductor device of claim 1 , wherein the memory layer is extended between the channel layer and the barrier patterns.

3. The semiconductor device of claim 1 , wherein the memory layer includes memory patterns that are separated from each other by the barrier patterns.

4. The semiconductor device of claim 1 , wherein, in each of the barrier patterns, an area that faces the insulating layers and an area that faces the channel layer are different.

5. The semiconductor device of claim 1 , wherein the barrier patterns include silicon nitride oxide, silicon oxide, or a combination thereof.

6. A semiconductor device comprising:

a gate structure with alternately stacked conductive layers and insulating layers;

a channel layer passing through the gate structure;

a tunnel insulating layer surrounding the channel layer;

a memory layer surrounding the tunnel insulating layer;

a blocking layer surrounding the memory layer; and

barrier patterns between the tunnel insulating layer and the insulating layers and separated from each other by the memory layer,

wherein each of the barrier patterns includes a first sidewall facing the memory layer, and the first sidewall is not straight.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2023
From: SEO, MOON SIK; YUN, DAE HWAN
To: SK HYNIX INC.
Reel/Frame 065485/0815 →
Priority Claims (1)
KR 10-2021-0017031 · Feb 5, 2021 · national
Continuity (2)
Division 17373142 · Jul 12, 2021
Related Publication 20240074198A1 · Feb 29, 2024
References Cited (4)
US 10177227B1 · Yoshida et al. · 2019 [cited by applicant]
KR 1020130092341A · 2013 [cited by applicant]
KR 1020140022204A · 2014 [cited by applicant]
KR 101756227B1 · 2017 [cited by applicant]