Granted Patent B2

US 12,204,408 · App. 18/154,164 · Granted Jan 21, 2025

Inventors: Ishwar Agarwal (Redmond, WA); George Zacharias Chrysos (Portland, WA); Oscar Rosell Martinez (Barcelona, ES)

Assignee: Microsoft Technology Licensing, LLC

G06F11/1068G06F3/0604G06F3/0619G06F3/0659G06F3/067G06F3/0679G06F11/1435G06F12/0811

Abstract

Claims (109)

1. A computer-implemented method of memory management, the method comprising:

receiving a request from a processor to read data corresponding to a system memory section from a cache of the processor;

retrieving, from a first section in a first memory, data and metadata, the metadata encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in a second memory;

analyzing the data location information in the retrieved metadata to determine that the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the first section in the first memory to the processor in response to the received request.

2. The computer-implemented method of claim 1 , further comprising:

receiving a second request to read data corresponding to the system memory section from a cache of the processor;

retrieving, from the first section in the first memory, second data and second metadata, the second metadata encoding data location information of multiple system memory sections in the first section of the first memory, the second section of the first memory, and one or more additional sections in the second memory; and

analyzing the data location information in the retrieved second metadata to determine that the first section in the first memory does not currently contain data corresponding to the system memory section in the received second request.

3. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received second request; and

retrieving the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received second request.

4. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; and

writing, to the first section in the first memory, the retrieved data from the second section in the first memory.

5. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

modifying the second metadata in the first memory to indicate that the data corresponding to the system memory section in the received second request is now in the first section of the first memory.

6. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

writing, to the second section in the first memory, the retrieved data from the first section of the first memory.

7. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory;

writing, to the second section in the first memory, the retrieved data from the first section of the first memory; and

modifying the second metadata in the first section of the first memory to indicate that:

the data corresponding to the system memory section in the received second request is now in the first section of the first memory; and

the data previously held in the first section of the first memory is now in the second section of the first memory.

8. The computer-implemented method of claim 1 , wherein:

the metadata includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more bits; and

determining whether the identified combination corresponds to the system memory section in the received request.

9. The computer-implemented method of claim 1 , wherein:

the metadata includes one or more Error Checking and Correction (ECC) bits; and

the data location information includes combinations of the one or more ECC bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more ECC bits; and

determining whether the identified combination of ECC bits corresponds to the system memory section in the received request.

10. A hardware memory controller configured to manage operations of a first memory and a second memory, the memory controller having instructions executable by the memory controller to perform operations comprising:

receiving a request from a processor to read data corresponding to a system memory section from a cache of the processor;

retrieving, from a first section in a first memory, data and metadata, the metadata encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in a second memory;

analyzing the data location information in the retrieved metadata to determine that the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the first section in the first memory to the processor in response to the received request.

11. The hardware memory controller of claim 10 , wherein:

the metadata includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more bits; and

determining whether the identified combination corresponds to the system memory section in the received request.

12. The hardware memory controller of claim 10 , wherein:

the metadata includes one or more Error Checking and Correction (ECC) bits; and

the data location information includes combinations of the one or more ECC bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more ECC bits; and

determining whether the identified combination of ECC bits corresponds to the system memory section in the received request.

13. The hardware memory controller of claim 10 , wherein the operations further comprise:

receiving a second request to read data corresponding to the system memory section from a cache of the processor;

retrieving, from the first section in the first memory, second data and second metadata, the second metadata encoding data location information of multiple system memory sections in the first section of the first memory, the second section of the first memory, and one or more additional sections in the second memory; and

analyzing the data location information in the retrieved second metadata to determine that the first section in the first memory does not currently contain data corresponding to the system memory section in the received second request.

14. The hardware memory controller of claim 13 , wherein the operations further comprise, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received second request; and

retrieving the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received second request.

15. The hardware memory controller of claim 13 , wherein the operations further comprise, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; and

writing, to the first section in the first memory, the retrieved data from the second section in the first memory.

16. The hardware memory controller of claim 13 , wherein the operations further comprise, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

modifying the second metadata in the first memory to indicate that the data corresponding to the system memory section in the received second request is now in the first section of the first memory.

17. The hardware memory controller of claim 13 , wherein the operations further comprise, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

writing, to the second section in the first memory, the retrieved data from the first section of the first memory.

18. The hardware memory controller of claim 13 , wherein the operations further comprise, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request:

further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory;

writing, to the second section in the first memory, the retrieved data from the first section of the first memory; and

modifying the second metadata in the first section of the first memory to indicate that:

the data corresponding to the system memory section in the received second request is now in the first section of the first memory; and

the data previously held in the first section of the first memory is now in the second section of the first memory.

19. A computer-implemented method of memory management, the method comprising:

receiving a request from a processor to read data corresponding to a system memory section from a cache of the processor;

retrieving, from a first section in a first memory, data and metadata, the metadata encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in a second memory;

analyzing the data location information in the retrieved metadata to determine that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request:

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received request; and

retrieving the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received request.

20. The computer-implemented method of claim 19 , wherein:

the metadata includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more bits; and

determining whether the identified combination corresponds to the system memory section in the received request.

Continuity (2)

References Cited (15)