Multiple plane programming with quick plane programming termination and lagging plane boosting

1. A memory device comprising:

a set of memory planes comprising a set of memory blocks; and

control logic, operatively coupled with the set of memory planes, to perform operations comprising:

executing a programming operation to program the set of memory blocks of the set of memory planes to a set of programming levels;

in response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, executing a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last program level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level; and

executing a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed programming.

2. The memory device of claim 1 , wherein the first program sub-operation comprises causing a set of programming pulses to be applied to the set of memory blocks.

3. The memory device of claim 2 , wherein following application of the set of programming pulses, the operations further comprise comparing a failed programming count corresponding to the last programming level for each of the memory planes of the set of memory planes to a threshold level to determine if a first condition is satisfied or a second condition is satisfied.

4. The memory device of claim 3 , wherein the first subset of one or more memory planes that passed programming are identified in response to determining the failed programming count satisfies the first condition; and wherein the second subset of one or more memory planes that failed programming are identified in response to determining the failed programming count satisfies the second condition.

5. The memory device of claim 1 , wherein the trim set is selected from a set of predefined trim sets.

6. The memory device of claim 1 , the operations further comprising updating a register value to mark the second subset of one or more memory planes as a lagging plane.

7. The memory device of claim 1 , wherein terminating the programming operation with respect to the first subset of one or more memory planes comprises preventing application of voltage to one or more wordlines associated with the first subset of one or more memory planes.

8. The memory device of claim 1 , wherein the trim set comprises one or more of a relaxed program loop limit setting, a maximum program voltage setting, a program pulse width setting, a program verify criteria setting, or a selective slow program convergence setting.

9. A memory device comprising:

a set of memory planes comprising a set of memory blocks; and

control logic, operatively coupled with the set of memory planes, to perform operations comprising:

initiating a multi-plane programming operation to program the set of memory blocks of the set of memory planes to a set of programming levels;

performing a program verify operation associated with a last programming level of the set of programming levels;

determining that a portion of a first memory block of the set of memory blocks pass the program verify operation;

causing a set of programming pulses to be applied to the set of memory blocks;

identifying a first subset of memory blocks that passed the program verify operation associated with the last programming level; and

terminating execution of the multi-plane programming operation on the first subset of memory blocks.

10. The memory device of claim 9 , the operations further comprising:

identifying a second subset of memory blocks that failed the program verify operation associated with the last programming level.

11. The memory device of claim 10 , the operations further comprising:

selecting a trim set from a set of trim sets; and

causing the trim set to be applied to the second subset of memory blocks.

12. The memory device of claim 9 , the operations further comprising:

determining a first count of memory bits of a first memory plane that failed programming; and

comparing the first count to a threshold level to determine a first condition is satisfied, wherein the first condition indicates that the first memory plane passed programming associated with the last programming level.

13. The memory device of claim 12 , the operations further comprising:

determining a second count of memory bits of a second memory plane that failed programming associated with the last programming level; and

comparing the second count to the threshold level to determine a second condition is satisfied, wherein the second condition indicates that the second memory plane failed programming associated with the last programming level.

14. A method comprising:

executing a programming operation to program a set of memory blocks of a set of memory planes to a set of programming levels;

in response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, executing a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level; and

executing a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation associated with the last programming level.

15. The method of claim 14 , wherein the first program sub-operation comprises causing a set of programming pulses to be applied to the set of memory blocks.

16. The method of claim 15 , wherein following application of the set of programming pulses, further comprising comparing a failed programming count corresponding to the last programming level for each of the memory planes of the set of memory planes to a threshold level to determine if a first condition is satisfied or a second condition is satisfied.

17. The method of claim 16 , wherein the first subset of one or more memory planes that passed the program verify operation associated with the last programming level are identified in response to determining the failed programming count satisfies the first condition; and wherein the second subset of one or more memory planes that failed the program verify operation associated with the last program level are identified in response to determining the failed programming count satisfies the second condition.

18. The method of claim 14 , wherein the trim set is selected from a set of predefined trim sets.

19. The method of claim 14 , further comprising updating a register value to mark the second subset of one or more memory planes as a lagging plane.

20. The method of claim 14 , wherein terminating the programming operation with respect to the first subset of one or more memory planes comprises preventing application of voltage to one or more wordlines associated with the first subset of one or more memory planes.