Communication logic to enhance area effectiveness for memory repair mechanism
According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.
1. A system for testing and repairing local memory in a hardware accelerator, the system comprising:
a one-time programmable (OTP) memory configured to sequentially store first repair data in a first partition and second repair data in a second partition for, respectively, a first subset of the local memory and a second subset of the local memory;
an OTP sequencer circuit configured to assert a first grant signal;
a first main-controller coupled to the OTP sequencer circuit and the first subset of the local memory, the first main-controller configured to:
first load the first repair data for the first subset of the local memory from the first partition, and
communicate a first status signal to the OTP sequencer circuit after completion of the first loading indicating a completion of the first loading, wherein the OTP sequencer circuit is further configured to de-assert the first grant signal in response to the OTP sequencer circuit receiving the first status signal and assert a second grant signal in response to the de-asserting of the first grant signal;
an offset addition and selection logic circuit configured to add an offset to an address used by a second main-controller to access the second partition; and
the second main-controller configured to:
second load the second repair data for the second subset of the local memory associated with the second main-controller from the second partition using the address to access the second partition, and
communicate a second status signal to the OTP sequencer circuit after completion of the second loading indicating a completion of the second loading, wherein the OTP sequencer circuit is further configured to de-assert the second grant signal in response to the OTP sequencer circuit receiving the second status signal.
2. The system of claim 1 , wherein the OTP sequencer circuit is configured to generate the first grant signal in response to the OTP sequencer circuit receiving a functional mode reset signal.
3. The system of claim 1 , further comprising a first repair controller coupled to the first main-controller and the OTP sequencer circuit, wherein the OTP sequencer circuit is configured to instruct the first main-controller to load the first repair data by the first repair controller in response to receiving the first grant signal.
4. The system of claim 1 , further comprising a second repair controller coupled to the second main-controller and the OTP sequencer circuit, wherein the OTP sequencer circuit is configured to instruct the second main-controller to load the second repair data by the second repair controller in response to receiving the second grant signal.
5. The system of claim 1 , wherein the hardware accelerator comprises a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), or a combination thereof.
6. The system of claim 1 , wherein the hardware accelerator is used for artificial intelligence or machine learning.
7. The system of claim 1 , wherein the second repair data is sequentially stored after the first repair data in the OTP memory such that the offset added to the address points to a memory space immediately after the first repair data.
8. A method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP), the method comprising:
asserting, by an OTP sequencer circuit, a first grant signal;
a first loading, by a first main-controller, of a first repair data for a first sub-set of the local memory associated with the first main-controller from a first partition of the OTP memory;
communicating, by the first main-controller, a first status signal to the OTP sequencer circuit after completion of the first loading indicating a completion of the first loading;
de-asserting, by the OTP sequencer circuit, the first grant signal in response to the OTP sequencer circuit receiving the first status signal;
asserting, by the OTP sequencer circuit, a second grant signal in response to the de-asserting of the first grant signal;
adding, by an offset addition and selection logic circuit, an offset to an address used by a second main-controller to access a second partition of the OTP memory comprising a second repair data, wherein the first repair data and the second repair data are sequentially loaded in the OTP memory;
a second loading, by the second main-controller, of the second repair data for a second sub-set of the local memory associated with the second main-controller from the second partition of the OTP memory using the address to access the second partition;
communicating, by the second main-controller, a second status signal to the OTP sequencer circuit after completion of the second loading indicating a completion of the second loading; and
de-asserting, by the OTP sequencer circuit, the second grant signal in response to the OTP sequencer circuit receiving the second status signal.
9. The method of claim 8 , wherein the first grant signal is generated in response to the OTP sequencer circuit receiving a functional mode reset signal.
10. The method of claim 8 , further comprising instructing the first main-controller to load the first repair data by a first repair controller in response to receiving the first grant signal, wherein the first repair controller is coupled to the first main-controller and the OTP sequencer circuit.
11. The method of claim 8 , further comprising instructing the second main-controller to load the second repair data by a second repair controller in response to receiving the second grant signal, wherein the second repair controller is coupled to the second main-controller and the OTP sequencer circuit.
12. The method of claim 8 , wherein the hardware accelerator comprises a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), or a combination thereof.
13. The method of claim 8 , wherein the hardware accelerator is used for artificial intelligence or machine learning.
14. The method of claim 8 , further comprising storing the second repair data sequentially after the first repair data in the OTP memory such that the offset added to the address points to a memory space immediately after the first repair data.
15. A system for testing and repairing local memory in a hardware accelerator, the system comprising:
a one-time programmable (OTP) memory configured to sequentially store first repair data in a first partition and second repair data in a second partition for, respectively, a first subset of the local memory and a second subset of the local memory;
a test control register (TCR) configured to assert a first grant signal;
a first main-controller coupled to the first subset of the local memory, the first main-controller configured to first load the first repair data for the first subset of the local memory from the first partition in response to the first grant signal being asserted;
an offset addition and selection logic circuit coupled to the TCR and the first main-controller, the offset addition and selection logic circuit configured to add an offset to an address used by a second main-controller to access the second partition, wherein the TCR is further configured to de-assert the first grant signal and assert a second grant signal in response to the de-asserting of the first grant signal; and
the second main-controller configured to second load the second repair data for the second subset of the local memory associated with the second main-controller from the second partition using the address to access the second partition in response to the second grant signal being asserted, wherein the TCR is further configured to de-assert the second grant signal.
16. The system of claim 15 , wherein the TCR is further configured to assert an access signal to operate the hardware accelerator in test mode.
17. The system of claim 15 , wherein the hardware accelerator comprises a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), or a combination thereof.
18. The system of claim 15 , wherein the hardware accelerator is used for artificial intelligence or machine learning.
19. The system of claim 15 , wherein the second repair data is sequentially stored after the first repair data in the OTP memory such that the offset added to the address points to a memory space immediately after the first repair data.
20. The system of claim 15 , further comprising a test access point (TAP) couplable to the TCR, the TAP configured to control operations of the TCR during a test mode operation of the hardware accelerator.