Semiconductor device, circuit board structure and manufacturing method thereof
A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
1. A semiconductor device, comprising:
a circuit board structure having a core layer, and a first build-up layer and a second build-up layer disposed on opposite sides of the core layer;
a plurality of first trenches penetrating through the first build-up layer and the core layer, and extending into a portion of the second build-up layer; and
an array of semiconductor chips bonded to the first build-up layer of the circuit board structure,
wherein the circuit board structure has a center region and a corner region, and the first trenches are arranged more in the corner region of the circuit board structure while arranged less in the center region of the circuit board structure.
2. The semiconductor device of claim 1 , wherein from a top view, the semiconductor chips are misaligned with the first trenches.
3. The semiconductor device of claim 1 , further comprising a plurality of second trenches penetrating through the second build-up layer and the core layer, and extending into a portion of the first build-up layer.
4. The semiconductor device of claim 3 , wherein from a top view, the semiconductor chips are misaligned with the second trenches.
5. The semiconductor device of claim 1 , further comprising a soft material in the first trenches.
6. The semiconductor device of claim 5 , further comprising an encapsulation layer disposed around the semiconductor structures and separated from the soft material in the first trenches.
7. The semiconductor device of claim 1 , further comprising a redistribution layer structure between the circuit board structure and each of the semiconductor chips.
8. A semiconductor device, comprising:
a circuit board structure having conductive regions and dielectric regions alternately arranged side by side;
a plurality of stress releasing trenches disposed in the dielectric regions of the circuit board structure; and
a plurality of semiconductor chips bonded to the conductive regions of the circuit board structure;
wherein from a top view, the semiconductor chips are misaligned with the stress releasing trenches.
9. The semiconductor device of claim 8 , further comprising an encapsulation layer around semiconductor chips and separated from the stress releasing trenches.
10. The semiconductor device of claim 8 , wherein the stress releasing trenches are configured to extend from opposite top and bottom sides of the circuit board structure.
11. The semiconductor device of claim 8 , wherein the circuit board structure is a device-free board structure.
12. The semiconductor device of claim 8 , wherein the circuit board structure is a coreless circuit board structure.
13. A semiconductor device, comprising:
a circuit board structure having a core layer, and a first build-up layer and a second build-up layer disposed on opposite sides of the core layer;
a first mask layer and a second mask layer disposed on the first build-up layer and the second build-up layer, respectively;
a plurality of first trenches penetrating through the first mask layer and the first build-up layer;
a plurality of second trenches penetrating through the second mask layer and the second build-up layer; and
an array of semiconductor chips bonded to the first build-up layer of the circuit board structure,
wherein from a top view, the semiconductor chips are misaligned with the second trenches.
14. The semiconductor device of claim 13 , further comprising a redistribution layer structure disposed between the first build-up layer and each of the semiconductor chips.
15. The semiconductor device of claim 14 , wherein a location of the first and second trenches is overlapped with a location of some conductive patterns of the redistribution layer structure.
16. The semiconductor device of claim 13 , wherein the first trenches and the second trenches further penetrate through the core layer.
17. The semiconductor device of claim 13 , further comprising a plurality of plated vias penetrating through the core layer, wherein the plated vias are electrically connect to the first build-up layer and the second build-up layer.
18. The semiconductor device of claim 13 , wherein the first trenches and the second trenches do not penetrate through the core layer.
19. The semiconductor device of claim 13 , wherein from a top view, the semiconductor chips are misaligned with the first trenches.
20. The semiconductor device of claim 13 , further comprising a soft material disposed in the first trenches and the second trenches, wherein a top surface of the soft material is flushed with a surface of the first mask layer or the second mask layer.