FinFET device having source/drain regions including a plurality of conductivity types and manufacturing method therefor
A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.
1. A semiconductor device, comprising:
a channel portion;
at least two channel structure portions disposed opposite the channel portion; and
source/drain regions disposed at both edges of the channel portion,
wherein the source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body, and
wherein impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.
2. The semiconductor device according to claim 1 , wherein the at least two channel structure portions each includes nano-wire structures.
3. The semiconductor device according to claim 2 , wherein at least two nano-wire structures are provided for each of the at least two channel structure portions.
4. The semiconductor device according to claim 2 , wherein the at least two channel structure portions each includes channel portions.
5. The semiconductor device according to claim 4 , wherein the at least two channel structure portions are made of silicon.
6. The semiconductor device according to claim 4 , wherein the at least two channel structure portions each further includes gate insulating films and a gate electrode.
7. The semiconductor device according to claim 6 , wherein the gate insulating films and the gate electrode are formed between a first channel portion and a second channel portion of the channel portions and embedded between the first channel portion and the second channel portion.
8. The semiconductor device according to claim 6 , wherein the gate insulating films each includes a first gate insulating film and a second gate insulating film.
9. The semiconductor device according to claim 8 , wherein the first gate insulating film is made of a silicon material and the second gate insulating film is made of a high dielectric constant material.
10. The semiconductor device according to claim 1 , wherein an impurity concentration C1 of the impurity layers is higher than an impurity concentration C2 of the semiconductor layers.
11. The semiconductor device according to claim 1 , wherein, when an impurity concentration of the impurity layer is denoted by C1 and an impurity concentration of the semiconductor layers is denoted by C2, an inequality represented by 0.1≤C2/C1≤10 is satisfied.
12. A manufacturing method for a semiconductor device, the semiconductor device including:
a channel portion;
at least two channel structure portions disposed opposite the channel portion; and
source/drain regions disposed at both edges of the channel portion,
wherein the method comprises:
subsequent to forming the channel portion, forming the at least two channel structure portions disposed opposite the channel portion;
subsequently, partially removing regions of a base body in which the source/drain regions are to be formed, in a thickness direction, to obtain source/drain region formation planned regions;
subsequently, forming, in the source/drain region formation planned regions, impurity layers having a second conductivity type; and
subsequently, forming, on the impurity layers, the source/drain regions including semiconductor layers having a first conductivity type different from the second conductivity type.
13. The manufacturing method for the semiconductor device, according to claim 12 , wherein the formation of the semiconductor layers on the impurity layers is based on an epitaxial growth method.
14. The manufacturing method for the semiconductor device, according to claim 12 , wherein the impurity layers are formed in the source/drain region formation planned regions on a basis of an ion implantation method.
15. The manufacturing method for the semiconductor device, according to claim 12 , wherein the at least two channel structure portions each includes nano-wire structures.
16. The manufacturing method for the semiconductor device, according to claim 15 , wherein at least two nano-wire structures are provided for each of the at least two channel structure portions.
17. The manufacturing method for the semiconductor device, according to claim 15 , wherein the at least two channel structure portions each includes channel portions.
18. The manufacturing method for the semiconductor device, according to claim 17 , wherein the at least two channel structure portions are made of silicon.
19. The manufacturing method for the semiconductor device, according to claim 17 , wherein the at least two channel structure portions each further includes gate insulating films and a gate electrode.
20. The manufacturing method for the semiconductor device, according to claim 19 , wherein the gate insulating films and the gate electrode are formed between a first channel portion and a second channel portion of the channel portions and embedded between the first channel portion and the second channel portion.