Bias generating devices and methods for generating bias
The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.
1. A bias voltage generating device, comprising: a reference bias circuit including a first diode-connected transistor pair and a second diode-connected transistor pair, wherein the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor, and the reference bias circuit is coupled to a first voltage and a second voltage; and a first transistor pair coupled to the reference bias circuit, the first transistor pair configured to provide a third voltage based on the first voltage and the second voltage, wherein gates of the diode-connected p-type transistor and the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a first transistor in the first transistor pair.
2. The bias voltage generating device of claim 1 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.
3. The bias voltage generating device of claim 1 , wherein: the first transistor is connected to receive the first voltage; the first diode-connected transistor pair is connected between a first impedance element and the second diode-connected transistor pair; and the second diode-connected transistor pair is connected between the first diode-connected transistor pair and a second impedance element.
4. The bias voltage generating device of claim 3 , wherein each of the first and second impedance elements includes a resistor, a long channel p-type MOSFET diode, and a long channel n-type MOSFET diode.
5. The bias voltage generating device of claim 4 , wherein:
the long channel p-type MOSFET diode includes a first p-type transistor and a second p-type transistor;
a gate of the first p-type transistor and a drain and a gate of the second p-type transistor are connected; and
a drain of the first p-type transistor and a source of the second p-type transistor are connected.
6. The bias voltage generating device of claim 4 , wherein:
the long channel n-type MOSFET diode includes a first n-type transistor and a second n-type transistor;
a drain and a gate of the first n-type transistor and a gate of the second n-type transistor are connected; and
a source of the first n-type transistor and a drain of the second n-type transistor are connected.
7. The bias voltage generating device of claim 3 , wherein each of the first and second impedance elements is formed by a resistor and a long channel MOSFET diode.
8. The bias voltage generating device of claim 1 , wherein: the first transistor pair further comprises comprising a second transistor connected to the first transistor; and, wherein the second transistor is configured to provide the third voltage based on the first voltage and the second voltage.
9. The bias voltage generating device of claim 8 , wherein gates of a diode-connected p-type transistor and a diode-connected n-type transistor of the second diode-connected transistor pair are connected to a gate of the second transistor.
10. The bias voltage generating device of claim 8 , wherein the third voltage is generated at a source of the first transistor and a source of the second transistor.
11. The bias voltage generating device of claim 1 , wherein a drain and a gate of the diode-connected p-type transistor are connected.
12. The bias voltage generating device of claim 1 , wherein a drain and a gate of the diode-connected n-type transistor are connected.
13. The bias voltage generating device of claim 1 , wherein a drain and a gate of the diode-connected p-type transistor and a drain and a gate of the diode-connected n-type transistor are connected.
14. The bias voltage generating device of claim 1 , wherein the third voltage is a portion of a difference between the first voltage and the second voltage.
15. A bias voltage generating device, comprising:
a reference bias section connected to a first voltage and a second voltage, the reference bias section comprising a first diode-connected transistor pair connected to the first voltage and a second diode-connected transistor pair connected to the second voltage, the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor; and
a driving section connected to the reference bias section, the driving section configured to provide a third voltage based on the first voltage and the second voltage, the driving section comprising a first transistor pair,
wherein gates of the diode-connected p-type transistor and the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a p-type transistor of the first transistor pair.
16. The bias voltage generating device of claim 15 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.
17. The bias voltage generating device of claim 15 , wherein: the first transistor pair is connected to receive the first voltage and the second voltage; the first diode-connected transistor pair is connected between a first impedance element and the second diode-connected transistor pair; and the second diode-connected transistor pair is connected between the first diode-connected transistor pair and a second impedance element.
18. The bias voltage generating device of claim 15 , wherein the first transistor pair includes an n-type transistor and the p-type transistor, and a source of the n-type transistor of the first transistor pair and a source of the p-type transistor of the first transistor pair are connected.
19. A method for operating a bias voltage generating circuit comprising: supplying a first voltage to a reference bias section and a driving section, wherein the reference bias section comprises a first diode-connected transistor pair and a second diode-connected transistor pair, the first diode-connected transistor pair is connected to the first voltage, the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor, and the driving section comprises a first transistor pair, and gates of the diode-connected p-type transistor and the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a n-type transistor of the first transistor pair; supplying a second voltage to the reference bias section and the driving section, wherein the second diode-connected transistor pair is connected to the second voltage; and providing a third voltage at the driving section based on the first voltage and the second voltage.
20. The method of claim 19 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.