IP Library › Granted Patent US 12,211,776
Granted Patent B2
US 12,211,776 · App. 17/574,944 · Granted Jan 28, 2025

Electronic package and manufacturing method thereof

Inventors: Chih-Hsien Chiu (Taichung, TW); Ko-Wei Chang (Taichung, TW); Wen-Jung Tsai (Taichung, TW); Che-Wei Yu (Taichung, TW); Chia-Yang Chen (Taichung, TW)
Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
H01L23/49816H01L21/4853H01L23/3121H01L24/16H01L24/81H01L25/0657H01L25/50H01L24/32H01L24/73H01L25/0652H01L2224/16227H01L2224/32225H01L2224/73204H01L2225/06517H01L2924/3511
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Quick Facts
Patent No.
US 12,211,776
App. No.
17/574,944
Granted
Jan 28, 2025
Kind
B2
Abstract

Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.

Claims (36)

1. An electronic package, comprising:

a carrier structure having a circuit layer and including a first side and a second side opposite to the first side;

conductive structures disposed on the first side of the carrier structure and electrically connected to the circuit layer;

an encapsulation layer formed on the first side of the carrier structure and covering the conductive structures, wherein portions of surfaces of the conductive structures are exposed from the encapsulation layer;

at least an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer; and

a metal frame disposed on the second side of the carrier structure, wherein the metal frame surrounds and covers the electronic component.

2. The electronic package of claim 1 , wherein each of the conductive structures includes a conductive pillar bonded to the circuit layer.

3. The electronic package of claim 2 , wherein the conductive pillar has an end face exposed from the encapsulation layer.

4. The electronic package of claim 2 , wherein the conductive pillar is bonded to the circuit layer via a conductor.

5. The electronic package of claim 1 , further comprising a functional pad embedded in the encapsulation layer, and the functional pad is bonded to the circuit layer.

6. The electronic package of claim 5 , wherein a portion of a surface of the functional pad is exposed from the encapsulation layer.

7. The electronic package of claim 1 , wherein each of the conductive structures includes a solder ball.

8. The electronic package of claim 7 , wherein the solder ball protrudes from the encapsulation layer.

9. The electronic package of claim 1 , wherein each of the conductive structures includes a circuit block.

10. The electronic package of claim 9 , wherein the circuit block includes at least one conductive pillar electrically connected to the circuit layer, and wherein the conductive pillar has an end face exposed from the encapsulation layer.

11. The electronic package of claim 9 , wherein the circuit block includes at least one circuit portion electrically connected to the circuit layer, and wherein a portion of a surface of the circuit portion is exposed from the encapsulation layer.

12. The electronic package of claim 1 , further comprising another electronic component embedded in the encapsulation layer and electrically connected to the circuit layer.

13. An electronic package, comprising:

a carrier structure having a circuit layer and including a first side and a second side opposite to the first side;

conductive structures disposed on the first side of the carrier structure and electrically connected to the circuit layer, wherein each of the conductive structures includes a circuit block;

an encapsulation layer formed on the first side of the carrier structure and covering the conductive structures, wherein portions of surfaces of the conductive structures are exposed from the encapsulation layer; and

at least an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer.

14. The electronic package of claim 13 , wherein the circuit block includes at least one conductive pillar electrically connected to the circuit layer, and wherein the conductive pillar has an end face exposed from the encapsulation layer.

15. The electronic package of claim 13 , wherein the circuit block includes at least one circuit portion electrically connected to the circuit layer, and wherein a portion of a surface of the circuit portion is exposed from the encapsulation layer.

16. An electronic package, comprising:

a carrier structure having a circuit layer and including a first side and a second side opposite to the first side;

conductive structures disposed on the first side of the carrier structure and electrically connected to the circuit layer;

an encapsulation layer formed on the first side of the carrier structure and covering the conductive structures, wherein portions of surfaces of the conductive structures are exposed from the encapsulation layer;

at least an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer; and

a metal stiffener disposed on the second side of the carrier structure.

17. An electronic package, comprising:

a carrier structure having a circuit layer and including a first side and a second side opposite to the first side, wherein a groove is formed on the first side of the carrier structure;

conductive structures disposed on the first side of the carrier structure and electrically connected to the circuit layer;

an encapsulation layer formed on the first side of the carrier structure and covering the conductive structures, wherein portions of surfaces of the conductive structures are exposed from the encapsulation layer;

at least an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer; and

another electronic component disposed in the groove and electrically connected to the circuit layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2022
From: CHIU, CHIH-HSIEN; CHANG, KO-WEI; TSAI, WEN-JUNG; YU, CHE-WEI; CHEN, CHIA-YANG
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 058645/0784 →
Priority Claims (2)
TW 110121187 · Jun 10, 2021 · national
TW 110134239 · Sep 14, 2021 · national
Continuity (1)
Related Publication 20230223322A1 · Jul 13, 2023
References Cited (3)
US 20170243826A1 · Lin · 2017 [cited by examiner]
US 20220223512A1 · Kuo · 2022 [cited by examiner]
US 20230044797A1 · Su · 2023 [cited by examiner]