Profile shaping for control gate recesses
Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.
1. A semiconductor structure comprising:
at least one pair of layers comprising a dielectric layer and a semiconductor layer, wherein the semiconductor layer comprises:
a first portion of the semiconductor layer characterized by a first etch rate for an etch treatment,
a second portion of the semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and
a third portion of the semiconductor layer characterized by a third etch rate that is greater than the second etch rate;
wherein the second portion is positioned between the first portion and the third portion, and the second portion of the semiconductor layer is characterized by a greater atomic percentage of phosphorous or nitrogen than the first portion or the third portion of the semiconductor layer and/or the second portion of the semiconductor layer is characterized by a higher amount of stress than the first portion or third portion of the semiconductor layer.
2. The semiconductor structure of claim 1 , wherein the dielectric layer comprises silicon oxide.
3. The semiconductor structure of claim 1 , wherein the semiconductor layer comprises doped polysilicon.
4. The semiconductor structure of claim 1 , wherein at least one pair of layers comprises greater than or about 50 pairs of layers.
5. The semiconductor structure of claim 1 , further comprising a second dielectric layer, wherein the semiconductor layer is formed between the dielectric layer and the second dielectric layer.
6. The semiconductor structure of claim 5 , wherein the dielectric layer, the second dielectric layer, or both the dielectric layer and the second dielectric layer comprise a silicon oxide having a silicon-to-oxygen ration of less than or about 1:7.
7. The semiconductor structure of claim 5 , wherein a side of the semiconductor layer is recessed from a side of the dielectric layer, the second dielectric layer, or both the dielectric layer and the second dielectric layer.
8. The semiconductor structure of claim 7 , wherein the semiconductor layer is characterized by a variation in a width of the semiconductor layer between a midpoint of the semiconductor layer and an end adjacent the dielectric layer, an end adjacent the second dielectric layer, or both, of less than or about 5 Å, wherein the width of the semiconductor layer extends from the recessed side to a second side.