Successive approximation register analog to digital converter having adaptive current or voltage parameter adjustments
Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
1. A device comprising:
a digital to analog conversion (DAC) circuit;
a comparator circuit coupled to the DAC circuit;
a set of storage circuits coupled to the comparator circuit and the DAC circuit, the set of storage circuits is configured to store a plurality of bits corresponding to an input voltage; and
a control circuit coupled to the comparator circuit, the control circuit configured to adjust a bias current used in the comparator circuit, a threshold voltage used in the comparator circuit, or a supply voltage used in the comparator circuit in response to a conversion margin, wherein the bias current, the threshold voltage, or the supply voltage is adjusted in response to a determined probability of a successful conversion, wherein the control circuit is configured to end adjustments when the current is above a minimum current value and the probability is in a mathematical relationship to a first threshold, when the threshold voltage is above a minimum threshold voltage and the probability is in the mathematical relationship to the first threshold, or when the supply voltage is above a minimum supply voltage and the probability is in the mathematical relationship to the first threshold.
2. The device of claim 1 , wherein the conversion margin is indicative of an amount of unused time before a bit error occurs within a sampling cycle.
3. The device of claim 1 , wherein the control circuit is configured to determine the conversion margin and adjust the bias current, the threshold voltage, or the supply voltage on a periodic basis.
4. The device of claim 1 , wherein the control circuit is configured to determine the conversion margin and adjust the bias current, the threshold voltage, or the supply voltage at device power-on.
5. The device of claim 1 , wherein the control circuit is configured to adjust the bias current and the threshold voltage.
6. The device of claim 1 , wherein the control circuit is configured to adjust the bias current in response to the conversion margin and the bias current is for a current mirror or a driver in the comparator circuit.
7. The device of claim 1 , wherein the control circuit is configured to adjust the threshold voltage in response to the conversion margin and the threshold voltage is used by a driver in the comparator circuit.
8. The device of claim 1 , wherein the control circuit is configured to adjust the supply voltage in response to the conversion margin.
9. The device of claim 1 , further comprising a conversion status circuit configured to provide a conversion status signal, where the conversion status circuit comprises a variable delay circuit, wherein the control circuit adjusts the variable delay circuit to determine the conversion margin.
10. An apparatus, comprising:
a receiver comprising:
an analog to digital conversion (ADC) circuit comprising:
a comparator; and
a processor configured to determine a conversion margin and adjust a current or voltage used in the comparator using the conversion margin, wherein the current or the voltage is adjusted in response to a determined probability of a successful conversion, wherein the successful conversion is defined when the conversion margin is greater than a second threshold, wherein the processor is configured to adjust the current when the current is above a minimum current value and the probability is above a first threshold, or wherein the processor is configured to adjust the voltage when the voltage is above a minimum voltage value and the probability is above the first threshold.
11. The apparatus of claim 10 , wherein the processor provides one or more select signals to a multiplexer in the comparator to adjust the current or the voltage.
12. The apparatus of claim 10 , wherein the processor is configured to adjust the current when the determined probability of the successful conversion is greater than the first threshold.
13. The apparatus of claim 10 , wherein the processor is configured to adjust the voltage when the determined probability of the successful conversion is greater than the first threshold.
14. The apparatus of claim 10 , wherein the processor is configured to adjust the voltage when the determined probability of the successful conversion is greater than the first threshold, wherein the voltage is a supply voltage for a driver in the comparator.
15. The apparatus of claim 10 , wherein the comparator and the processor are provided and the processor is a microprocessor, on on-chip integrated logic circuit, or an analog correction loop circuit in an integrated circuit package.
16. An apparatus, comprising:
a receiver comprising:
an analog to digital conversion (ADC) circuit comprising:
a comparator; and
a processor configured to determine a conversion margin and adjust a current or voltage used in the comparator using the conversion margin, wherein the processor is configured to determine a probability of a successful conversion is greater than a first threshold and end adjustments when the current is above a minimum current value and the probability is approximately equal to the first threshold.
17. The apparatus of claim 16 , wherein the successful conversion is defined when the conversion margin is greater than a second threshold, the processor is configured to adjust the current when the current is above the minimum current value and the probability is above the first threshold, or, the processor is configured to adjust the voltage when the voltage is above a minimum voltage value and the probability is above the first threshold.
18. A method comprising:
sampling an input voltage by a comparator coupled to a digital to analog converter;
determining, by the comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the input voltage, wherein the comparator has a current parameter or voltage parameter adjusted based upon a conversion margin, wherein adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits, wherein the current parameter or the voltage parameter is adjusted in response to a determined probability of a successful conversion, wherein the successful conversion is defined when the conversion margin is greater than a second threshold, wherein the current parameter is adjusted when the current parameter is above a minimum current value and the probability is above a first threshold, or wherein the voltage parameter is adjusted when the voltage parameter is above a minimum voltage value and the probability is above the first threshold; and
storing the bits in the set of the storage circuits.
19. The method of claim 18 , wherein the conversion margin is related to a delay value determined in response to a sample clock and at least one enable signal for the storage circuits coupled to the comparator.
20. The apparatus of claim 16 , wherein is defined when the conversion margin is greater than a second threshold.