Nanostructures formed over a substrate and a gate structure wrapping around the nanostructures
A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion directly below the gate spacer layer and a second portion directly below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.
1. A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a hard mask layer over the first fin structure and the second fin structure;
patterning the hard mask layer to form a trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer;
removing a portion of the first fin structure and a portion of the second fin structure to form a first S/D recess and a second S/D recess; and
forming a first source/drain (S/D) structure in the first S/D recess and a second S/D structure in the second S/D recess.
2. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a first oxide layer over the first fin structure and the second fin structure before forming the hard mask layer;
forming the hard mask layer over the first oxide layer;
forming the gate spacer layer in the trench;
removing a portion of the gate spacer layer and a portion of the first oxide layer exposed by the trench; and
removing a portion of a topmost first semiconductor layer to form a recess.
3. The method for forming the semiconductor device structure as claimed in claim 2 , further comprising:
forming a second oxide layer over the hard mask layer, wherein the hard mask layer is between the first oxide layer and the second oxide layer.
4. The method for forming the semiconductor device structure as claimed in claim 2 , further comprising:
forming a dummy gate dielectric layer in the recess, wherein the dummy gate dielectric layer is in direct contact with the topmost first semiconductor layer.
5. The method for forming the semiconductor device structure as claimed in claim 4 , further comprising:
removing the dummy gate electrode layer;
removing the dummy gate dielectric layer to form a trench;
removing the second semiconductor layers to form a gap; and
forming a gate structure in the trench and the gap.
6. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a dielectric feature between the first fin structure and the second fin structure, wherein the dielectric feature comprises a cap layer above the first fin structure, and the hard mask layer is over the cap layer.
7. The method for forming the semiconductor device structure as claimed in claim 6 , further comprising:
forming a first oxide layer over the cap layer;
forming the hard mask layer over the first oxide layer; and
removing the first oxide layer before forming the first S/D recess and the second S/D recess.
8. A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a dielectric feature between the first fin structure and the second fin structure;
forming a hard mask layer over the first fin structure and the second fin structure;
patterning the hard mask layer to form a trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer;
removing the dummy gate electrode layer to form trench;
removing the second semiconductor layers to form a gap; and
forming a gate structure in the trench and the gap.
9. The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
removing a portion of the first semiconductor layers to form notches; and
forming inner spacer layers in the notches.
10. The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
forming a dielectric layer on the dielectric feature and the gate structure; and
forming a gate contact structure through the dielectric layer, wherein the gate contact structure is electrically connected to the gate structure.
11. The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
forming a cladding layer on the first fin structure and the second fin structure before forming the dielectric feature.
12. The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
removing a portion of a topmost first semiconductor layer to form a recess; and
forming a dummy gate dielectric layer in the recess.
13. The method for forming the semiconductor device structure as claimed in claim 8 , wherein the dielectric feature comprises a cap layer, wherein a top surface of the cap layer is higher than a top surface of the gate structure.
14. The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
forming a first oxide layer over the first fin structure and the second fin structure before forming the hard mask layer over the first fin structure and the second fin structure.
15. A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a first oxide layer over the first fin structure and the second fin structure;
forming a hard mask layer on the first oxide layer;
patterning the hard mask layer to form a trench;
removing a portion of the first oxide layer exposed by the trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer; and
replacing the dummy gate electrode layer with a gate structure.
16. The method for forming the semiconductor device structure as claimed in claim 15 , further comprising:
removing a portion of a topmost first semiconductor layer to form a recess; and
forming a dummy gate dielectric layer in the recess.
17. The method for forming the semiconductor device structure as claimed in claim 15 , further comprising:
forming a cladding layer on the first fin structure and the second fin structure; and
removing the cladding layer before replacing the dummy gate electrode layer with the gate structure.
18. The method for forming the semiconductor device structure as claimed in claim 15 , further comprising:
forming a dielectric feature between the first fin structure and the second fin structure, wherein the dielectric features comprises a liner layer, a filling layer and a cap layer on the liner layer and the filling layer.
19. The method for forming the semiconductor device structure as claimed in claim 18 , further comprising:
forming the hard mask layer on the dielectric feature.
20. The method for forming the semiconductor device structure as claimed in claim 15 , further comprising:
removing the second semiconductor layers to form nanostructures; and
forming the gate structure surrounding the nanostructures.