Enhanced input of machine-learning accelerator activations
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations on a machine-learning accelerator having multiple tiles. The apparatus includes a processor having a plurality of tiles and scheduling circuitry that is configured to select a respective input activation for each tile of the plurality of tiles from either an activation line for the tile or a delay register for the activation line.
1. A method performed using a processor comprising a plurality of activation lines and a plurality of delay registers, wherein each delay register is paired with a respective activation line, the method comprising:
on a first global tick, populating a first delay register with a first activation value from a first activation line of the processor, and
routing a second activation value to the first activation line;
on a first local tick of the first global tick, providing at least the first activation value from the delay register to a compute tile of the processor; and
on each subsequent local tick of the first global tick, providing one or more additional activation values from the plurality of activation lines after providing at least the first activation value from the delay register.
2. The method of claim 1 , wherein on each local tick of the first global tick, performing, by the processor, a mathematical operation between an input activation value and a respective weight to generate a partial sum value.
3. The method of claim 2 , wherein the mathematical operation is part of a convolution operation, and wherein the respective weights are from a convolution kernel.
4. The method of claim 2 , comprising computing, by the processor, an accumulated sum at least in part from the partial sum value and an additional partial sum value.
5. The method of claim 1 , further comprising, on a second global tick, populating one or more delay registers with one or more third activation values from the plurality of activation lines, and reading, from a memory device, one or more fourth activation values onto the plurality of activation lines.
6. The method of claim 5 , wherein the memory device comprises static random-access memory.
7. The method of claim 1 , comprising determining each activation value based on a stride length.
8. The method of claim 7 , wherein the stride length is based on a size of a convolution kernel.
9. The method of claim 1 , wherein providing one or more additional activation values from the plurality of activation lines comprises:
determining whether there are more partial sums for the first global tick; and
computing a subsequent partial sum with fewer delay registers when there are more partial sums for the first global tick, or determining whether there are more global ticks when there are no more partial sums for the first global tick.
10. The method of claim 9 , comprising overwriting the plurality of delay registers when there are more global ticks, or ending a process when there are no more global ticks.