Semiconductor devices with backside air gap dielectric
A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
1. A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain epitaxial features;
two metal plugs through the isolation structure and contacting two of the source/drain epitaxial features from the backside; and
a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
2. The semiconductor structure of claim 1 , wherein side portions of the dielectric liner directly contact the two metal plugs, and the side portions vary in thickness to form an over-hang profile.
3. The semiconductor structure of claim 1 , wherein a side portion of the dielectric liner closer towards the backside is thicker than another side portion of the dielectric liner further from the backside.
4. The semiconductor structure of claim 1 , wherein a top portion of the air gap closer to the backside is narrower than a middle portion of the air gap further from the backside.
5. The semiconductor structure of claim 1 , wherein side portions of the dielectric liner have a thickness in a range from about 0.5 nm to 10 nm, and the space between the two metal plugs has a width in a range from about 10 nm to about 500 nm.
6. The semiconductor structure of claim 1 ,
wherein the one or more transistors further includes an active region between the two source/drain epitaxial features,
wherein the space between the two metal plugs is wider than a width of the active region in a cross-section view cut along a first direction from one of the two metal plugs to another one of the two metal plugs.
7. The semiconductor structure of claim 6 , wherein the two source/drain epitaxial features and the active region are each separated from the air gap by a bottom portion of the dielectric liner.
8. The semiconductor structure of claim 7 , wherein the bottom portion of the dielectric liner has a thickness in a range from about 0.5 nm to 10 nm in a vertical direction.
9. The semiconductor structure of claim 1 , wherein the dielectric liner partially surrounds the air gap, further comprising:
an interconnect structure over the dielectric liner and the metal plugs and at the backside, wherein the interconnect structure and the dielectric liner collectively fully surround the air gap.
10. The semiconductor structure of claim 1 , wherein the dielectric liner fully surrounds the air gap.
11. The semiconductor structure of claim 1 , wherein the dielectric liner includes a low-k dielectric material having Si, O, N, or C.
12. A semiconductor structure, comprising:
a semiconductor feature;
an isolation structure disposed on sidewalls of the semiconductor feature;
a gate structure disposed on sidewalls and a top surface of the semiconductor feature and on a top surface of the isolation structure;
first and second source/drain features sandwiching the semiconductor feature;
first and second metal plugs through the isolation structure and contacting bottom surfaces of the first and second source/drain features, respectively; and
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the first and second metal plugs, wherein an air gap between the first and second metal plugs is partially or fully surrounded by the dielectric liner.
13. The semiconductor structure of claim 12 , wherein a middle portion of the dielectric liner is thinner than both a topmost portion and a bottommost portion of the dielectric liner.
14. The semiconductor structure of claim 12 , wherein the dielectric liner includes a porous dielectric material.
15. The semiconductor structure of claim 12 , further comprising:
a first interconnect structure over the gate structure and the first and second source/drain features; and
a second interconnect structure under the dielectric liner and the first and second metal plugs, wherein the second interconnect structure and the dielectric liner together fully surrounds the air gap.
16. The semiconductor structure of claim 15 , wherein the second interconnect structure includes:
a metal line directly contacting one of the metal plugs; and
a dielectric layer over the dielectric liner and the air gap, and the dielectric layer is exposed in the air gap.
17. A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain electrodes;
two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside;
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the two metal plugs; and
an interconnect structure over the dielectric liner at the backside,
wherein an air gap between the two metal plugs is sealed by the dielectric liner and the interconnect structure.
18. The semiconductor structure of claim 17 , wherein a first portion of the dielectric liner is thicker than a second portion of the dielectric liner, wherein the first portion of the dielectric liner is more towards the backside than the second portion of the dielectric liner.
19. The semiconductor structure of claim 17 , wherein a bottom portion of the dielectric liner directly lands on each of the two source/drain electrodes.
20. The semiconductor structure of claim 17 , wherein a bottom portion of the dielectric liner directly lands on an active region of the one or more transistors, and the active region is disposed between the two source/drain electrodes.