IP Library › Granted Patent US 12,225,707
Granted Patent B2
US 12,225,707 · App. 17/819,817 · Granted Feb 11, 2025

Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory

Inventors: Xingsong Su (Hefei, CN); Weiping Bai (Hefei, CN); Deyuan Xiao (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10B12/038H10B12/37
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Quick Facts
Patent No.
US 12,225,707
App. No.
17/819,817
Granted
Feb 11, 2025
Kind
B2
Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Claims (49)

1. A method for manufacturing a semiconductor structure, comprising:

providing a substrate;

patterning the substrate to form a substrate layer and a plurality of silicon pillars;

forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars;

forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars;

forming a first conductive layer in the gaps;

partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and

forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

2. The method according to claim 1 , wherein the patterning the substrate to form a substrate layer and a plurality of silicon pillar comprises:

forming a first mask layer on the substrate, wherein the first mask layer has a first pattern extending in a first direction;

transferring the first pattern to part of the substrate by taking the first mask layer as a mask;

forming a second mask layer on the substrate, wherein the second mask layer has a second pattern extending in a second direction; and

transferring the second pattern to part of the substrate by taking the second mask layer as a mask to form the substrate layer and the plurality of silicon pillars.

3. The method according to claim 1 , wherein the patterning the substrate to form a substrate layer and a plurality of silicon pillars comprises:

forming a third mask layer on the substrate, the third mask layer comprising a plurality of sub-masks arranged in an array, and the third mask layer having a third pattern composed of a first pattern extending in a first direction and a second pattern extending in a second direction; and

transferring the third pattern to part of the substrate by taking the third mask layer as a mask to form the substrate layer and the plurality of silicon pillars.

4. The method according to claim 1 , wherein the forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars comprises:

forming an initial oxide layer on surfaces of the plurality of silicon pillars and a surface of the substrate layer between the plurality of silicon pillars; and

removing the initial oxide layer on the surfaces of the plurality of silicon pillars, remaining initial oxide layer forming the oxide layer.

5. The method according to claim 1 , wherein the forming an isolation structure on the oxide layer comprises:

forming a first isolation structure on a surface of the oxide layer; and

forming a second isolation structure on the first isolation structure, the gaps being provided between the second isolation structure and the silicon pillars, and the first isolation structure and the second isolation structure constituting the isolation structure.

6. The method according to claim 5 , wherein the forming a first isolation structure on a surface of the oxide layer comprises:

forming an initial first isolation structure on the surface of the oxide layer and a surface of each of the silicon pillars; and

partially removing the initial first isolation structure, remaining initial first isolation structure on the surface of the oxide layer forming the first isolation structure.

7. The method according to claim 5 , wherein the forming a second isolation structure on the first isolation structure comprises:

forming sacrificial layers on surfaces the plurality of silicon pillars;

forming an initial second isolation structure on surfaces of the sacrificial layers and on the first isolation structure;

removing the initial second isolation structure above a plane where top surfaces of the sacrificial layers are located, remaining initial second isolation structure forming the second isolation structure; and

removing the sacrificial layers to form the gaps between the isolation structure and the silicon pillars.

8. The method according to claim 5 , wherein the partially removing the isolation structure comprises:

removing the second isolation structure and removing the first isolation structure below the second isolation structure, retaining the first isolation structure below the first conductive layer.

9. The method according to claim 7 , wherein the sacrificial layers are formed by thermal oxidation.

10. The method according to claim 1 , wherein the forming a first conductive layer in the gaps comprises:

forming an initial first conductive layer in the gaps and on top surfaces of the plurality of silicon pillars and the isolation structure; and

removing the initial first conductive layer above a plane where top surfaces of the silicon pillars are located, remaining initial first conductive layer forming the first conductive layer.

11. The method according to claim 10 , during the removing the initial first conductive layer above a plane where top surfaces of the silicon pillars are located, further comprising:

removing the isolation structure located above the plane where the top surfaces of the silicon pillars are located.

12. The method according to claim 1 , wherein the forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars comprises:

forming the dielectric layer on the surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars; and

forming the second conductive layer on a surface of the dielectric layer.

13. The method according to claim 12 , wherein the second conductive layer completely fills gaps of the dielectric layer.

14. The method according to claim 1 , wherein materials of the first isolation structure and the second isolation structure are the same.

15. The method according to claim 1 , wherein a bottom of the isolation structure completely covers the oxide layer.

16. The method according to claim 1 , wherein sides of a bottom of the isolation structure are in direct contact with adjacent silicon pillars.

17. The method according to claim 1 , wherein the first conductive layer is used to form a lower electrode of the semiconductor structure, and the second conductive layer is used to form an upper electrode of the semiconductor structure.

18. The method according to claim 1 , wherein the plurality of silicon pillars are arranged in an array.

19. A semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to claim 1 .

20. A semiconductor memory comprising the semiconductor structure according to claim 19 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: SU, XINGSONG; BAI, WEIPING; XIAO, DEYUAN
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 060810/0015 →
Priority Claims (1)
CN 202210316932.1 · Mar 28, 2022 · national
Continuity (2)
Continuation PCTCN2022099844 · Jun 20, 2022
Related Publication 20230328955A1 · Oct 12, 2023
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