Granted Patent B2

US 12,229,060 · App. 17/554,400 · Granted Feb 18, 2025

Inventor: Dmitri Yudanov (Rancho Cordova, CA)

Assignee: Micron Technology, Inc.

G06F13/1668G06F13/4027

Abstract

Claims (58)

1. An apparatus, comprising:

a memory module, having:

a first bus in the memory module;

a plurality of memory chips connected to the first bus;

a first controller coupled to the first bus;

a second controller coupled to the first bus, wherein the second controller comprises at least one graphics processing unit (GPU); and

at least one interface device coupled to the first bus and configured to communicate input and output data for the memory module; and

facilitate communication among a plurality of instances of the memory module generated via a global shared context implemented by the memory module to facilitate processing of the data proximate to the memory module by the GPU;

at least one arbiter configured to:

queue memory requests to each of the plurality of memory chips for the data; and

resolve at least one conflict when a processor outside of the memory module attempts to access the data in the plurality of memory chips while the first or second controller is accessing the plurality of memory chips;

wherein the first bus is connectable as a part of a second bus to which the processor outside of the memory module is connected; and

wherein the least one interface device is configured to bypass the second bus and the processor.

2. The apparatus of claim 1 , wherein the interface device is configured to communicate the input and output data to at least one other instance of the apparatus, bypassing a second bus connected to a processor in a system in which the apparatus is installed; and the first bus is connectable to the second bus.

3. The apparatus of claim 1 , comprising:

a plurality of electrical contacts; and

a printed circuit board (PCB) configured for insertion into at least one memory slot of a motherboard;

and wherein:

the plurality of memory chips is coupled to the PCB;

the plurality of electrical contacts is on each side of the PCB;

the at least one special-purpose controller is coupled to the PCB; and

the at least one interface device is coupled to the PCB.

4. The apparatus of claim 1 , wherein the at least one interface device comprises at least one wireless interface device that communicates at least in part wirelessly.

5. The apparatus of claim 1 , wherein the least one interface device is configured to bypass the second bus and the processor when communicating the input and output data for the memory module.

6. A system, comprising:

a plurality of dual in-line memory modules (DIMMs), each DIMM of the plurality of DIMMs, comprising:

a printed circuit board (PCB) configured for insertion into at least one memory slot of an additional PCB that is separate from the plurality of DIMMs;

a plurality of memory chips coupled to the PCB;

a plurality of electrical contacts on each side of the PCB;

at least one special-purpose controller coupled to the PCB, wherein the at least one special-purpose controller of at least one DIMM of the plurality of DIMMs comprises at least one graphics processing unit (GPU); and

at least one interface device configured to:

communicate input and output data for the DIMM, wherein the input and output data bypasses at least one processor of a computing device in which the system is installed; and

facilitate communication among a plurality of instances of the plurality of DIMMs generated via a global shared context implemented by the DIMMs to facilitate processing of the data proximate to the DIMMs by the GPU; and

at least one arbiter configured to:

queue memory requests to each of the plurality of DIMMs for the data; and

resolve at least one conflict when the at least one processor attempts to access the data in the plurality of memory chips while at least one special- purpose controller is accessing the plurality of memory chips.

7. The system of claim 6 , wherein the at least one interface device is configured to communicate the input and output data to at least one other DIMM of the plurality of DIMMs.

8. The system of claim 6 , comprising:

at least one external controller that is separate from the plurality of DIMMs and that is configured to:

coordinate computations by the special-purpose controllers of the plurality of DIMMs; and

coordinate communications by the interface devices of the plurality of DIMMs; and

the additional PCB, wherein the additional PCB is separate from the plurality of DIMMs and comprises a plurality of memory slots configured to receive the plurality of DIMMs, wherein the at least one external controller is coupled to the additional PCB, and wherein the additional PCB is a motherboard and the at least one external controller comprises at least one central processing unit (CPU).

9. The system of claim 6 , wherein the at least one interface device of at least one DIMM of the plurality of DIMMs comprises intra-chip optical interconnect.

10. The system of claim 9 , wherein, for each DIMM of the plurality of DIMMs, the at least one wireless interface device of the DIMM is configured to receive input data for the at least one special-purpose controller and communicate output data of the at least one special-purpose controller to one or more user interfaces via one or more wireless communication links that bypass the at least one processor of the computing device in which the system is installed.

11. A memory module, comprising:

a plurality of memory chips;

at least one special-purpose controller, wherein the at least one special-purpose controller of at least comprises at least one graphics processing unit (GPU); and

at least one interface device configured to communicate input and output data for the memory module, wherein the input and output data bypasses at least one processor of a computing device in which the memory module is installed, and wherein the at least one interface device is configured to:

communicate the input and output data to at least one other memory module in the computing device; and

facilitate communication among a plurality of instances of the memory module generated via a global shared context implemented by the memory module to facilitate processing of the data proximate to the memory module by the GPU;

at least one arbiter configured to:

queue memory requests to each of the plurality of memory chips for the data; and

resolve at least one conflict when the at least one processor attempts to access the data in the plurality of memory chips while the at least one special-purpose controller is accessing the plurality of memory chips.

12. The memory module of claim 11 , wherein the one interface device is a network interface device configured to communicate input and output data of the at least one special-purpose controller over one or more communication networks.

13. The memory module of claim 11 , wherein the at least one special-purpose controller comprises at least one artificial intelligence (AI) accelerator.

14. The memory module of claim 11 , wherein the at least one special-purpose controller comprises at least one processing-in-memory (PIM) unit.

15. The memory module of claim 11 , wherein the at least one interface device comprises at least one wireless interface device configured to communicate at least in part wirelessly over one or more wireless communication networks, and wherein the one or more wireless communication networks bypass at least one data bus of the computing device in which the memory module is installed.

16. The memory module of claim 11 , wherein the least one interface device is configured to bypass the at least one processor when communicating the input and output data for the memory module.

Assignments (1)

Continuity (2)

References Cited (50)