Systems, apparatus and methods for rapid peripheral component interconnect express (PCIE) system boot
In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.
1. An apparatus comprising:
a plurality of cores to execute instructions;
a firmware agent to execute a first firmware;
a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link, wherein the PCIe interface is to receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware; and
a boot agent coupled to the PCIe interface via a sideband link, the boot agent to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface.
2. The apparatus of claim 1 , wherein the boot agent comprises a local storage, the local storage including a first load buffer and a second load buffer.
3. The apparatus of claim 2 , wherein the boot agent is to store a first portion of the PCIe firmware in the first load buffer and send the first portion to the PCIe interface while a second portion of the PCIe firmware is stored into the second load buffer.
4. The apparatus of claim 1 , wherein the boot agent is to configure the sideband link to operate in a quad mode.
5. The apparatus of claim 1 , wherein the boot agent is to cause the PCIe interface to boot up in less than 120 milliseconds to enable the PCIe interface to receive a configuration cycle for enumeration.
6. The apparatus of claim 1 , wherein the apparatus comprises a system on chip (SoC) having the plurality of cores.
7. The apparatus of claim 6 , wherein the apparatus comprises an add-in card, the add-in card comprising the SoC, wherein the SoC is configured as a network accelerator.
8. The apparatus of claim 7 , wherein the boot agent is to download the PCIe firmware prior download of the first firmware in response to a determination that the SoC is to be configured as the network accelerator.
9. The apparatus of claim 6 , wherein the SoC comprises a peripheral controller hub, the peripheral controller hub comprising the boot agent.
10. The apparatus of claim 6 , wherein in response to a determination that the SoC is to be configured as a host device, the boot agent is to provide the PCIe firmware to the PCIe interface after the first firmware is provided to the firmware agent.
11. A non-transitory computer readable medium comprising instructions that when executed enable a system to:
determine that a device comprising a system on chip (SoC) is configured as a Peripheral Component Interconnect Express (PCIe) endpoint;
in response to the determination, load, via a boot agent, a first firmware portion of a firmware of the SoC from a non-volatile storage and provide the first firmware portion to a PCIe interface of the SoC;
after provision of the first firmware portion to the PCIe interface, enable the PCIe interface to begin operation; and
in response to a receipt of a fundamental reset signal assertion, load one or more additional firmware portions of the firmware of the SoC from the non-volatile storage.
12. The non-transitory computer readable medium of claim 11 , further comprising instructions that when executed cause the system to reconfigure a sideband link coupled between the boot agent and the PCIe interface to a higher speed prior to provision of the first firmware portion to the PCIe interface.
13. The non-transitory computer readable medium of claim 11 , further comprising instructions that when executed cause the system to load all of the firmware of the SoC prior to enabling the PCIe interface in response to a determination that the device is not configured as the PCIe endpoint.
14. The non-transitory computer readable medium of claim 11 , further comprising instructions that when executed cause the system to:
store a first portion of a PCIe firmware in a first load buffer; and
send the first portion from the first load buffer to the PCIe interface while a second portion of the PCIe firmware is stored into a second load buffer.
15. The non-transitory computer readable medium of claim 11 , further comprising instructions that when executed cause the system authenticate the firmware and in response to the authentication, to load the first firmware portion.
16. A system comprising:
a host device comprising at least one first system on chip (SoC) to execute instructions, the at least one first SoC comprising a first plurality of cores and a first Peripheral Component Interconnect Express (PCIe) interface;
a peripheral device coupled to the host device via a PCIe link, the peripheral device comprising at least one second SoC comprising a second plurality of cores and a second PCIe interface, wherein the second SoC is configured as a network accelerator, the first SoC and the second SoC having an identical hardware configuration; and
at least one non-volatile memory to store a first firmware for the host device and a second firmware for the peripheral device, wherein a boot agent is to prioritize provision of a PCIe firmware portion of the second firmware to enable the peripheral device to comply with a PCIe enumeration boot time parameter.
17. The system of claim 16 , wherein the boot agent is to prioritize the PCIe firmware provision in response a determination that the second SoC is to be configured as the network accelerator.
18. The system of claim 16 , wherein the second SoC comprises the boot agent.
19. The system of claim 16 , wherein the second PCIe interface is to receive a configuration cycle within 120 milliseconds from a power good indication.