Integrated chiplet-based central processing units with accelerators for video processing
In some embodiments, a method includes receiving, at a central processing unit (CPU)-based demultiplexer of a CPU, an input video data stream; performing, at the CPU, an accelerator decoding configuration assessment of an accelerator decoding configuration of an accelerator; and based upon the accelerator decoding configuration assessment, dynamically decoding CPU-based demultiplexer output from the CPU-based demultiplexer using a CPU-based decoding unit and an accelerator-based decoding unit. In some embodiments of the method, the accelerator decoding configuration assessment includes performing an accelerator-based decoding unit hardware configuration assessment of the accelerator-based decoding unit and a CPU-based decoding unit software configuration assessment of the CPU-based decoding unit software utilized for the CPU-based decoding unit.
1 . A system-on-chip, comprising:
a central processing unit (CPU)-based demultiplexer;
a CPU-based decoding unit and an accelerator-based decoding unit coupled to the CPU-based demultiplexer via a die-to-die interconnect; and
an accelerator-based preprocessing unit coupled to the CPU-based decoding unit and the accelerator-based decoding unit via the die-to-die interconnect, wherein based upon an accelerator decoding configuration assessment, the system-on-chip utilizes the CPU-based decoding unit and the accelerator-based decoding unit to dynamically decode CPU-based demultiplexer output from the CPU-based demultiplexer for video processing;
wherein the accelerator decoding configuration assessment comprises an accelerator-based decoding unit hardware configuration assessment that includes determining whether the CPU-based demultiplexer output maps to an accelerator-based decoding unit hardware configuration of the accelerator-based decoding unit.
2 . The system-on-chip of claim 1 , wherein:
the accelerator decoding configuration assessment further comprises a CPU-based decoding unit software configuration assessment.
3 . The system-on-chip of claim 2 , wherein:
the CPU-based decoding unit software configuration assessment includes determining whether the CPU-based demultiplexer output maps to a CPU-based decoding unit software configuration of the CPU-based decoding unit.
4 . The system-on-chip of claim 3 , wherein:
the system-on-chip is configured to utilize the accelerator-based preprocessing unit to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.
5 . The system-on-chip of claim 4 , wherein:
the system-on-chip utilizes an accelerator-based preprocessing unit configuration assessment to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.
6 . The system-on-chip of claim 5 , wherein:
the accelerator-based processing unit configuration assessment includes an accelerator-based preprocessing unit hardware configuration assessment and a CPU-based preprocessing unit software configuration assessment.
7 . The system-on-chip of claim 6 , further comprising:
an accelerator-based encoding unit coupled to the accelerator-based preprocessing unit, wherein the system-on-chip is configured to utilize the accelerator-based encoding unit to dynamically encode preprocessing output from the accelerator-based preprocessing unit.
8 . The system-on-chip of claim 7 , wherein:
the system-on-chip utilizes an accelerator-based encoding unit hardware configuration assessment to dynamically encode preprocessor output from the accelerator-based preprocessing unit.
9 . A system-on-chip, comprising:
a central processing unit (CPU)-based demultiplexer;
a CPU-based decoding unit and an accelerator-based decoding unit coupled to the CPU based demultiplexer via a die-to-die interconnect; and
an accelerator-based preprocessing unit coupled to the CPU-based decoding unit and the accelerator-based decoding unit via the die-to-die interconnect, wherein based upon an accelerator decoding configuration assessment, the system-on-chip utilizes the CPU-based decoding unit and the accelerator-based decoding unit to dynamically decode CPU-based demultiplexer output from the CPU-based demultiplexer for video processing;
wherein the accelerator decoding configuration assessment comprises a CPU-based decoding unit software configuration assessment that includes determining whether the CPU-based demultiplexer output maps to a CPU-based decoding unit software configuration of the CPU-based decoding unit.
10 . The system-on-chip of claim 9 , wherein the accelerator decoding configuration assessment further comprises an accelerator-based decoding unit hardware configuration assessment.
11 . The system-on-chip of claim 10 , wherein the accelerator-based decoding unit hardware configuration assessment that includes determining whether the CPU-based demultiplexer output maps to an accelerator-based decoding unit hardware configuration of the accelerator-based decoding unit.
12 . The system-on-chip of claim 9 , wherein the system-on-chip is configured to utilize the accelerator-based preprocessing unit to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.
13 . The system-on-chip of claim 12 , wherein the system-on-chip utilizes an accelerator-based preprocessing unit configuration assessment to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.
14 . The system-on-chip of claim 13 , wherein the accelerator-based processing unit configuration assessment includes an accelerator based preprocessing unit hardware configuration assessment and a CPU-based preprocessing unit software configuration assessment.
15 . The system-on-chip of claim 14 , further comprising:
an accelerator-based encoding unit coupled to the accelerator-based preprocessing unit, wherein the system-on-chip is configured to utilize the accelerator-based encoding unit to dynamically encode preprocessing output from the accelerator based preprocessing unit.
16 . The system-on-chip of claim 15 , wherein:
the system-on-chip utilizes an accelerator-based encoding unit hardware configuration assessment to dynamically encode preprocessor output from the accelerator-based preprocessing unit.
17 . A system-on-chip, comprising:
a central processing unit (CPU)-based demultiplexer;
a CPU-based decoding unit and an accelerator-based decoding unit coupled to the CPU based demultiplexer via a die-to-die interconnect; and
an accelerator-based preprocessing unit coupled to the CPU-based decoding unit and the accelerator-based decoding unit via the die-to-die interconnect, wherein based upon an accelerator decoding configuration assessment, the system-on-chip utilizes the CPU-based decoding unit and the accelerator-based decoding unit to dynamically decode CPU-based demultiplexer output from the CPU-based demultiplexer for video processing;
wherein the system-on-chip is configured to utilize the accelerator-based preprocessing unit to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.
18 . The system-on-chip of claim 17 , wherein the accelerator decoding configuration assessment further comprises an accelerator-based decoding unit hardware configuration assessment and a CPU-based decoding unit software configuration assessment.
19 . The system-on-chip of claim 18 , wherein the CPU-based decoding unit software configuration assessment includes determining whether the CPU-based demultiplexer output maps to a CPU-based decoding unit software configuration of the CPU-based decoding unit.
20 . The system-on-chip of claim 17 , wherein the accelerator-based processing unit configuration assessment includes an accelerator-based preprocessing unit hardware configuration assessment and a CPU-based preprocessing unit software configuration assessment.