Memory device including memory cells and edge cells
View Patent ↗A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
1. A memory device, comprising:
an array of memory cells;
at least one first edge cell; and
at least one second edge cell, wherein
the at least one first edge cell and the at least one second edge cell are arranged respectively at two opposite sides of the array of memory cells, and
at least one edge cell, among the at least one first edge cell and the at least one second edge cell, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
2. The memory device of claim 1 , wherein each edge cell of the at least one first edge cell and the at least one second edge cell comprises:
a pair of transistors whose gates are coupled to each other and coupled to a word line of each edge cell.
3. The memory device of claim 2 , wherein:
the pair of transistors are p-type metal-oxide-semiconductor (PMOS) transistors;
sources of the pair of transistors are coupled to a positive power supply voltage; and
drains of the pair of transistors are coupled to a power header supply voltage for controlling the array of memory cells to enter or exit the power down mode.
4. The memory device of claim 3 , wherein:
when the word line of the edge cell switches to a logic high power level, the array of memory cells enters the power down mode; and
when the word line of the edge cell switches to a logic low power level, the array of memory cells exits the power down mode.
5. The memory device of claim 2 , wherein:
the pair of transistors are n-type metal-oxide-semiconductor (NMOS) transistors;
sources of the pair of transistors are coupled to a power footer supply voltage for controlling the array of memory cells to enter or exit the power down mode; and
drains of the pair of transistors are coupled to a negative power supply voltage.
6. The memory device of claim 5 , wherein:
when the word line of the edge cell switches to a logic low power level, the array of memory cells enters the power down mode; and
when the word line of the edge cell switches to a logic high power level, the array of memory cells exits the power down mode.
7. The memory device of claim 2 , wherein voltages of the word lines of the at least one first edge cells and the at least one second edge cell are controlled by a common power management signal.
8. The memory device of claim 1 , wherein:
each first edge cell of the at least one first edge cell comprises a pair of PMOS transistors whose gates are coupled to each other and coupled to a word line of the at least one first edge cell; and
each second edge cell of the at least one second edge cell comprises a pair of NMOS transistors whose gates are coupled to each other and coupled to a word line of the at least one second edge cell.
9. The memory device of claim 7 , wherein:
sources of the pair of PMOS transistors are coupled to a positive power supply voltage of the at least one first edge cell;
drains of the pair of PMOS transistors are coupled to a power header supply voltage of the at least one first edge cell;
sources of the pair of NMOS transistors are coupled to a power footer supply voltage of the at least one second edge cell; and
drains of the pair of NMOS transistors are coupled to a negative power supply voltage of the at least one second edge cell.
10. The memory device of claim 7 , wherein:
a voltage of the word line of each first edge cell is controlled by a power management signal and a delay circuit; and
a voltage of the word line of each second edge cell is controlled by the power management signal and an invertor circuit.
11. A static random access memory (SRAM) chip, comprising:
an array of SRAM cells;
at least one first edge cell; and
at least one second edge cell, wherein
the at least one first edge cell and the at least one second edge cell are arranged respectively at two opposite sides of the array of SRAM cells, and
at least one edge cell, among the at least one first edge cell and the at least one second edge cell, comprises a power switch configured for controlling a power supply to the array of SRAM cells.
12. The SRAM chip of claim 11 , wherein each edge cell of the at least one first edge cell and the at least one second edge cell comprises:
a pair of transistors whose gates are coupled to each other and coupled to a word line of each edge cell.
13. The SRAM chip of claim 12 , wherein:
the pair of transistors are p-type metal-oxide-semiconductor (PMOS) transistors;
sources of the pair of transistors are coupled to a positive power supply voltage;
drains of the pair of transistors are coupled to a power header supply voltage;
when the word line of the edge cell switches to a logic high power level, the array of SRAM cells enters a power down mode; and
when the word line of the edge cell switches to a logic low power level, the array of SRAM cells exits the power down mode.
14. The SRAM chip of claim 12 , wherein:
the pair of transistors are n-type metal-oxide-semiconductor (NMOS) transistors;
sources of the pair of transistors are coupled to a power footer supply voltage;
drains of the pair of transistors are coupled to a negative power supply voltage;
when the word line of the edge cell switches to a logic low power level, the array of SRAM cells enters a power down mode; and
when the word line of the edge cell switches to a logic high power level, the array of SRAM cells exits the power down mode.
15. The SRAM chip of claim 12 , wherein voltages of the word lines of the at least one first edge cell and the at least one second edge cell are controlled by a common power management signal.
16. The SRAM chip of claim 11 , wherein:
each first edge cell of the at least one first edge cell comprises a pair of PMOS transistors whose gates are coupled to each other and coupled to a word line of each first edge cell;
sources of the pair of PMOS transistors are coupled to a positive power supply voltage of each first edge cell;
drains of the pair of PMOS transistors are coupled to a power header supply voltage of the first edge cell;
each second edge cell of the at least one second edge cell comprises a pair of NMOS transistors whose gates are coupled to each other and coupled to a word line of each second edge cell;
sources of the pair of NMOS transistors are coupled to a power footer supply voltage of each second edge cell; and
drains of the pair of NMOS transistors are coupled to a negative power supply voltage of each second edge cell.
17. The SRAM chip of claim 16 , wherein:
a voltage of the word line of each first edge cell is controlled by a power management signal and a delay circuit; and
a voltage of the word line of each second edge cell is controlled by the power management signal and an invertor circuit.
18. A method for operating a device that includes: an array of memory cells and a plurality of edge cells, comprising:
generating an activated sleep signal;
shifting a first word line, coupled to a power header edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the activated sleep signal;
turning off at least one first transistor in the power header edge cell in response to shifting the first word line;
shifting a second word line, coupled to a power footer edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the activated sleep signal;
turning off at least one second transistor in the power footer edge cell in response to shifting the second word line; and
switching the array of memory cells from a normal power mode to a power down mode based on turning off the at least one first transistor and the at least one second transistor.
19. The method of claim 18 , wherein:
the power header edge cell and the power footer edge cell are arranged respectively at two opposite sides of the array of memory cells;
a gate of the at least one first transistor is coupled to the word line;
a source of the at least one first transistors is coupled to a positive power supply voltage;
a drain of the at least one first transistor is coupled to a power supply to the array of memory cells;
a gate of the at least one second transistor is coupled to to the word line;
a source of the at least one second transistor is coupled to a power supply to the array of memory cells; and
a drain of the at least one second transistor is coupled to a negative power supply voltage.
20. The method of claim 18 , further comprising:
generating a deactivated sleep signal;
shifting the first word line, coupled to the power header edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the deactivated sleep signal;
turning on the at least one first transistor in the power header edge cell;
shifting the second word line, coupled to the power footer edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the deactivated sleep signal;
turning on the at least one second transistor in the power footer edge cell; and
switching the array of memory cells from the power down mode to the normal power mode based on turning on the at least one first transistor and the at least one second transistor.