Semiconductor package and method of fabricating the same
Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.
1. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern; and
a redistribution pattern on a top surface of the under-bump pattern,
wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the bottom surface of the under-bump pattern is at a level higher than a level of a bottom surface of the dielectric layer,
wherein the under-bump seed pattern does not extend onto any of a top surface of the dielectric layer and the bottom surface of the under-bump pattern.
2. The semiconductor package of claim 1 , wherein a difference between the level of the bottom surface of the under-bump pattern and the level of the bottom surface of the dielectric layer is 80% to 120% of a thickness of the under-bump seed pattern.
3. The semiconductor package of claim 1 , wherein the top surface of the under-bump pattern has a downwardly convex shape.
4. The semiconductor package of claim 1 , wherein the under-bump pattern extends onto a top surface of the under-bump seed pattern.
5. The semiconductor package of claim 1 , wherein:
the top surface of the under-bump pattern is at a level the same as or lower than a level of a top surface of the under-bump seed pattern, and
the dielectric layer covers the top surface of the under-bump seed pattern.
6. The semiconductor package of claim 1 , wherein the redistribution pattern includes a wiring part and a via part between the wiring part and the under-bump pattern, and
wherein a thickness of the under-bump pattern is greater than a thickness of the wiring part.
7. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern; and
a redistribution pattern on a top surface of the under-bump pattern,
wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the bottom surface of the under-bump pattern is at a level higher than a level of a bottom surface of the dielectric layer,
wherein a first angle between the bottom surface and the sidewall of the under-bump pattern is an obtuse angle.
8. The semiconductor package of claim 7 , further comprising an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern.
9. The semiconductor package of claim 8 , wherein the dielectric layer exposes a bottom surface of the under-bump seed pattern, and
wherein the bottom surface of the under-bump seed pattern is at a level higher than a level of the bottom surface of the under-bump pattern.
10. The semiconductor package of claim 8 , wherein a difference between the level of the bottom surface of the under-bump pattern and the level of the bottom surface of the dielectric layer is 80% to 120% of a thickness of the under-bump seed pattern.
11. The semiconductor package of claim 7 , wherein the first angle ranges from 110° to 140°.
12. The semiconductor package of claim 7 , further comprising:
a molding layer on the redistribution substrate, the molding layer covering the semiconductor chip;
an upper redistribution layer on the molding layer; and
a conductive structure between the redistribution substrate and the upper redistribution layer, the conductive structure being laterally spaced apart from the semiconductor chip.
13. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern; and
a redistribution pattern on a top surface of the under-bump pattern,
wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the top surface of the under-bump pattern has a downwardly convex shape,
wherein the under-bump seed pattern does not extend onto any of a top surface of the dielectric layer and the bottom surface of the under-bump pattern.
14. The semiconductor package of claim 13 , wherein a difference between a level of the bottom surface of the under-bump pattern and a level of a bottom surface of the dielectric layer is 80% to 120% of a thickness of the under-bump seed pattern.
15. The semiconductor package of claim 13 , wherein the under-bump pattern extends onto a top surface of the under-bump seed pattern.
16. The semiconductor package of claim 13 , wherein:
the top surface of the under-bump pattern is at a level the same as or lower than a level of a top surface of the under-bump seed pattern, and
the dielectric layer covers the top surface of the under-bump seed pattern.