Reducing RC delay in semiconductor devices
The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
1. A method, comprising:
forming a first dielectric layer over a transistor;
forming a second dielectric layer on the first dielectric layer;
forming a contact structure through the first and second dielectric layers, wherein the contact structure is in contact with the transistor;
forming a first cavity in the first dielectric layer and adjacent to the contact structure;
forming a second cavity in the second dielectric layer and above the first cavity; and
forming a liner on a first inner surface of the first cavity and on a second inner surface of the second cavity.
2. The method of claim 1 , wherein forming the contact structure comprises:
forming a first conductive structure on a source/drain region of the transistor and in the first dielectric layer; and
forming a second conductive structure on the first conductive structure and in the second dielectric layer.
3. The method of claim 1 , further comprising forming, before forming the second dielectric layer, an etch stop layer on the first dielectric layer.
4. The method of claim 3 , wherein forming the second cavity comprises forming an opening through the etch stop layer and connecting the first and second cavities.
5. The method of claim 3 , wherein forming the liner comprises depositing the liner on an upper surface and a lower surface of the etch stop layer.
6. The method of claim 1 , wherein forming the first cavity comprises removing a portion of the first dielectric layer above a gate structure of the transistor.
7. The method of claim 1 , wherein forming the first cavity comprises forming curved internal surfaces of the first cavity.
8. A method, comprising:
forming a first dielectric layer over a transistor;
forming an etch stop layer on the first dielectric layer;
forming a second dielectric layer on the etch stop layer;
forming a contact structure through the first and second dielectric layers and the etch stop layer, wherein the contact structure is in contact with a source/drain region of the transistor;
forming an air gap adjacent to the contact structure and in the first and second dielectric layers; and
forming a liner in the air gap, wherein the liner is in contact with a top surface of the air gap.
9. The method of claim 8 , wherein forming the air gap comprises forming rounded corners of the air gap.
10. The method of claim 8 , wherein forming the air gap comprises:
forming a first cavity in the first dielectric layer;
forming a second cavity in the second dielectric layer; and
forming an opening through the etch stop layer and connecting the first and second cavities.
11. The method of claim 8 , wherein forming the air gap comprises forming the air gap above a gate structure of the transistor.
12. The method of claim 8 , wherein forming the liner comprises depositing the liner on an upper surface and a lower surface of the etch stop layer.
13. The method of claim 8 , wherein forming the liner comprises depositing the liner on a slanted surface of the air gap.
14. The method of claim 8 , wherein forming the liner comprises depositing the liner on a convex bottom surface of the air gap.
15. A method, comprising:
forming a dielectric layer over a transistor;
forming a contact structure through the dielectric layer and in contact with a source/drain region of the transistor;
forming a first cavity in the dielectric layer and adjacent to the contact structure;
forming a second cavity under the first cavity and connected to the first cavity through an opening; and
reducing a size of the opening.
16. The method of claim 15 , wherein reducing the size of the opening comprises forming a liner on inner surfaces of the first and second cavities.
17. The method of claim 15 , wherein forming the dielectric layer comprises forming an etch stop layer between the first and second cavities.
18. The method of claim 17 , wherein forming the second cavity comprises forming the opening through the etch stop layer.
19. The method of claim 15 , further comprising forming a liner on inner surfaces of the first and second cavities.
20. The method of claim 15 , further comprising forming an other contact structure through the dielectric layer and in contact with a gate structure of the transistor, wherein forming the first cavity comprises removing a portion of the dielectric layer above the gate structure and away from the other contact structure.