Field-effect transistors having a gate electrode positioned inside a substrate recess
Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.
1. A structure comprising:
a semiconductor substrate including a first surface, a first recess in the first surface, and a second surface inside the first recess;
a shallow trench isolation region extending from the first surface into the semiconductor substrate, the shallow trench isolation region positioned to surround an active device region including the first recess; and
a field-effect transistor including a gate electrode positioned on a portion of the second surface and a gate dielectric layer on the second surface, the gate dielectric layer positioned between the gate electrode and the portion of the second surface, and the gate dielectric layer including a first section with a first thickness and a second section with a second thickness that is greater than the first thickness.
2. The structure of claim 1 wherein the gate electrode includes a first portion having a first thickness on the first section of the gate dielectric layer and a second portion having a second thickness on the second section of the gate dielectric layer that is less than the first thickness.
3. The structure of claim 1 wherein the semiconductor substrate includes a second recess in the second surface, and the first section of the gate dielectric layer is positioned in the second recess.
4. The structure of claim 1 wherein the field-effect transistor includes a source/drain region laterally positioned in the semiconductor substrate between the first recess and the shallow trench isolation region.
5. The structure of claim 1 wherein the semiconductor substrate includes a third surface inside the first recess, the third surface inclined at a first angle from the second surface to the first surface of the semiconductor substrate, and the gate electrode is laterally offset from the third surface.
6. The structure of claim 5 wherein the semiconductor substrate includes a fourth surface inside the first recess, the second surface is positioned between the third surface and the fourth surface, the fourth surface inclined at a second angle from the second surface to the first surface of the semiconductor substrate, and the gate electrode is laterally offset from the fourth surface.
7. The structure of claim 6 wherein the gate electrode is laterally positioned between the third surface and the fourth surface.
8. The structure of claim 1 wherein the first recess has a first width, and the gate electrode has a second width that is less than the first width.
9. The structure of claim 8 wherein the active device region has a third width, and the first width of the first recess is less than the third width.
10. The structure of claim 1 wherein the first recess has a first width, the active device region has a second width, and the first width of the first recess is less than the second width.
11. A structure comprising:
a semiconductor substrate including a first surface, a recess in the first surface, and a second surface inside the recess;
a shallow trench isolation region extending from the first surface into the semiconductor substrate, the shallow trench isolation region positioned to surround an active device region including the recess;
a field-effect transistor including a gate electrode positioned on a portion of the second surface; and
a polycrystalline layer in the semiconductor substrate, the polycrystalline layer positioned beneath the active device region and the recess.
12. The structure of claim 11 wherein the polycrystalline layer abuts the shallow trench isolation region.
13. The structure of claim 11 wherein the semiconductor substrate includes a third surface inside the recess, the third surface inclined at a first angle from the second surface to the first surface of the semiconductor substrate, and the gate electrode is laterally offset from the third surface.
14. The structure of claim 13 wherein the semiconductor substrate includes a fourth surface inside the recess, the second surface is positioned between the third surface and the fourth surface, the fourth surface inclined at a second angle from the second surface to the first surface of the semiconductor substrate, and the gate electrode is laterally offset from the fourth surface.
15. The structure of claim 14 wherein the gate electrode is laterally positioned between the third surface and the fourth surface.
16. A method comprising:
forming a first dielectric layer on a first surface of a semiconductor substrate;
patterning the first dielectric layer to form an opening extending to the first surface;
oxidizing the semiconductor substrate at a location of the opening to form a second dielectric layer that is faceted;
removing the second dielectric layer to form a first recess in the first surface of the semiconductor substrate, wherein the semiconductor substrate includes a second surface inside the first recess;
forming a shallow trench isolation region extending from the first surface into the semiconductor substrate, wherein the shallow trench isolation region is positioned to surround an active device region including the first recess; and
forming a field-effect transistor including a gate electrode positioned on a portion of the second surface.
17. The method of claim 16 wherein the field-effect transistor includes a gate dielectric layer formed between the gate electrode and the portion of the second surface.
18. The method of claim 17 wherein the gate dielectric layer includes a first section with a first thickness and a second section with a second thickness that is greater than the first thickness.
19. The method of claim 18 further comprising:
forming a second recess in the second surface, wherein the first section of the gate dielectric layer is positioned in the second recess.
20. The method of claim 18 wherein the first recess has a first width, the gate electrode has a second width that is less than the first width, the active device region has a third width, and the first width of the first recess is less than the third width.